ADV7180
Timing Signals Output Enable
Table 14. DR_STR_C Function
TIM_OE, Address 0x04 [3]
DR_STR_C[1:0]
Description
00
Low drive strength (1×)
Medium-low drive strength (2×)
Medium-high drive strength (3×)
High drive strength (4×)
The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active state (that is, driving state) even if the
TOD bit is set. If TIM_OE is set to low, the HS, VS, and FIELD
pins are three-stated depending on the TOD bit. This
functionality is beneficial if the decoder is to be used as a
timing generator only. This may be the case if only the timing
signals are to be extracted from an incoming signal, or if the
part is in free-run mode, where a separate chip can output a
company logo, for example.
01 (default)
10
11
Drive Strength Selection (Sync)
DR_STR_S[1:0], Address 0xF4 [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and FIELD are
driven. For more information, refer to the Drive Strength
Selection (Data) section.
For more information on three-state control, refer to the
Three-State Output Drivers section and the Three-State LLC
Driver section.
Table 15. DR_STR_S Function
DR_STR_S[1:0]
Description
Individual drive strength controls are provided via the
DR_STR_XX bits.
00
Low drive strength (1×)
Medium-low drive strength (2×)
Medium-high drive strength (3×)
High drive strength (4×)
01 (default)
10
11
When TIM_OE is 0 (default), HS, VS, and FIELD are three-
stated according to the TOD bit.
Enable Subcarrier Frequency Lock Pin
When TIM_OE is 1, HS, VS, and FIELD are forced active all the
time.
EN_SFL_PIN, Address 0x04 [1]
Drive Strength Selection (Data)
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as Genlock) from the ADV7180 core
to an encoder in a decoder/encoder back-to-back arrangement.
DR_STR[1:0], Address 0xF4 [5:4]
For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.
When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.
When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.
For more information on three-state control, refer to the Drive
Strength Selection (Clock) and the Drive Strength Selection
(Sync) sections.
Polarity LLC Pin
PCLK, Address 0x37 [0]
Table 13. DR_STR Function
DR_STR[1:0]
Description
The polarity of the clock that leaves the ADV7180 via the LLC
pin can be inverted using the PCLK bit.
00
Low drive strength (1×)
Medium-low drive strength (2×)
Medium-high drive strength (3×)
High drive strength (4×)
01 (default)
10
11
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
Drive Strength Selection (Clock)
When PCLK is 0, the LLC output polarity is inverted.
DR_STR_C[1:0], Address 0xF4 [3:2]
When PCLK is 1 (default), the LLC output polarity is normal
(see the Timing Specifications section).
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the Drive Strength Selection (Sync) and the Drive
Strength Selection (Data) sections.
Rev. A | Page 20 of 112
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