ADV7174/ADV7179
ANALOG SIGNAL INTERCONNECT
SUPPLY DECOUPLING
The ADV7174/ADV7179 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 μF ceramic capacitor decoupling. Each group
of VAA pins on the ADV7174/ADV7179 must have at least one
0.1 μF decoupling capacitor to GND. These capacitors should
be placed as close to the device as possible.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
It is important to note that while the ADV7174/ADV7179
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to
reducing power supply noise and consider using a 3-terminal
voltage regulator for supplying power to the analog power
plane.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7174/ADV7179 to minimize
reflections.
DIGITAL SIGNAL INTERCONNECT
The ADV7174/ADV7179 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
The digital inputs to the ADV7174/ADV7179 should be
isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
The circuit in Figure 55 can be used to generate a 13.5 MHz
HSYNC
waveform using the 27 MHz clock and the
pulse. This
waveform is guaranteed to produce the 13.5 MHz clock in
synchronization with the 27 MHz clock. This 13.5 MHz clock
can be used if the 13.5 MHz clock is required by the MPEG
decoder. This guarantees that the Cr and Cb pixel information
is input to the ADV7174/ADV7179 in the correct sequence.
Due to the high clock rates involved, long clock lines to the
ADV7174/ADV7179 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not to the
analog power plane.
Note that the exposed metal paddle on the bottom side of the
LFCSP package must be soldered to PCB ground for proper
heat dissipation and also for electrical noise and mechanical
strength benefits.
D
Q
13.5MHz
D
Q
CLOCK
HSYNC
CK
CK
Figure 55. Circuit to Generate 13.5 MHz
Rev. B | Page 40 of 52
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