ADV7174/ADV7179
CGMS_WSS REGISTER 1 (C/W1)
Bits:
Address :
C/W17–C/W10
SR4–SR0 = 17H
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52 shows the operations under the control of this register.
C/W17
C/W16
C/W15
C/W14
C/W13
C/W12
C/W11
C/W10
C/W17 – C/W16
CGMS DATA BITS
C/W15 – C/W10
CGMS/WSS DATA BITS
Figure 52. CGMS_WSS Register 1
Table 19. C/W1 Bit Description
Bit Name
Bit No.
Description
CGMS/WSS Data Bits
C/W15–C/W10
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these bits
are CGMS data. In PAL mode, these bits are WSS data.
CGMS Data Bits
C/W17–C/W16
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 (C/W2)
Bits:
C/W27–C/W20
Address:
(SR4–SR00) = 18H
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53 shows the operations under the control of this register.
C/W27
C/W26
C/W25
C/W24
C/W23
C/W22
C/W21
C/W20
C/W27 – C/W20
CGMS/WSS DATA BITS
Figure 53. CGMS_WSS Register 2
Table 20. C/W2 Bit Description
Bit Name
Bit No.
C/W27–C/W20
Description
CGMS/WSS Data Bits
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these
bits are CGMS data. In PAL mode, these bits are WSS data.
Rev. B | Page 38 of 52
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