ADV7174/ADV7179
is disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Pixel data is latched on
the rising clock edge following the timing signal transitions.
Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL).
HSYNC BLANK
, FIELD
Mode 1: Master Option
,
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
SYNC and odd/even FIELD signals. A transition of the FIELD
HSYNC BLANK
Figure 26 illustrates the
,
, and FIELD for an
HSYNC
BLANK
input when
retrace. The
is low indicates a new frame, i.e., vertical
odd or even field transition relative to the pixel data.
BLANK
signal is optional. When the
input
HSYNC
FIELD
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Rev. B | Page 21 of 52
ADI [ ADI ]
