ADV7174/ADV7179
CLOCK
COMPOSITE
VIDEO
(e.g., VCR
OR CABLE)
SCRESET/RTC
VIDEO
DECODER
(e.g., ADV7183A)
GREEN/LUMA/Y
RED/CHROMA/Pr
P7–P0
BLUE/COMPOSITE/Pb
HSYNC
FIELD/VSYNC
AD7174/ADV7179
SEQUENCE
RESERVED
2
BIT
H/LTRANSITION
COUNT START
RESET
BIT
5 BITS
RESERVED
4 BITS
RESERVED
3
LOW
13
14 BITS
RESERVED
128
1
PLL INCREMENT
F
SC
0
0
21
RTC
TIME SLOT: 01
6768
14
19
NOT USED IN THE
ADV7174/ADV7179
VALID
SAMPLE SAMPLE
INVALID
8/LLC
NOTES
1
F
F
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 F DDS REGISTER IS
SC
SC
PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
SC
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET BIT
3
RESET ADV7174/ADV7179 DDS
Figure 19. RTC Timing and Connections
Vertical Blanking Data Insertion
nization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace.
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre-/post-
equalization pulses (see Figure 21 to Figure 32). This mode of
operation is called partial blanking and is selected by setting
MR32 to 1. It allows the insertion of any VBI data (opened VBI)
into the encoded output waveform. This data is present in the
digitized incoming YCbCr data stream, for example. WSS data,
CGMS, VPS, and so on. Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines by setting MR32
to 0.
HSYNC
VSYNC
Mode 0 is illustrated in Figure 20. The
BLANK
, FIELD/
,
and
mode.
(if not used) pins should be tied high during this
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7174/ADV7179 generates H, V, and F signals required
for the SAV and EAV time codes in the CCIR-656 standard. The
HSYNC
H bit is output on the
pin, the V bit is output on the
BLANK
VSYNC
pin.
pin, and the F bit is output on the FIELD/
Mode 0 (CCIR-656): Slave Option
Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
The H, V, and F transitions relative to the video waveform are
illustrated in Figure 23.
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7174/ADV7179 is controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchro-
Rev. B | Page 17 of 52
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