ADV7127
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D1
D2
D3
D4
D5
D6
D7
D8
1
2
3
4
5
6
7
8
24
23
22
21
20
Data Sheet
D0
PSAVE
R
SET
V
REF
COMP
TOP VIEW
(Not to Scale)
ADV7127
19
I
OUT
18
17
16
15
14
13
I
OUT
V
AA
GND
GND
CLOCK
14959-003
D9
9
V
AA 10
PDOWN
11
DNC
12
DNC = DO NOT CONNECT
DNC
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1 to 9,
24
10, 17
11
12, 13
14
Mnemonic
D0 to D9
Description
Data Inputs (TTL-Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit.
Unused data inputs are connected to either the regular printed circuit board (PCB) power or ground plane. Data
inputs are red, green, or blue pixel inputs.
Analog Power Supply (5 V ± 5%). All V
AA
pins on the
must be connected.
Power-Down Control Pin. The
completely powers down, including the voltage reference circuit, when
PDOWN is low.
Do Not Connect. Do not connect to these pins.
Clock Input (TTL-Compatible). The rising edge of CLOCK latches D0 to D9 where D0 to D9 can be red, green, or
blue pixel data inputs (TTL-compatible). CLOCK is typically the pixel clock rate of the video system. CLOCK is driven
by a dedicated TTL buffer.
Ground. All GND pins must be connected.
Differential Current Output. This pin is capable of directly driving a doubly terminated 75 Ω load. If not required,
this output is tied to ground.
Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω coaxial
cable.
Compensation Pin. COMP is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and V
AA
.
Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an external
resistor divider network is not recommended. A 0.1 μF decoupling ceramic capacitor is connected between V
REF
and V
AA
.
Full-Scale Adjust Control. A resistor (R
SET
) connected between this pin and GND controls the magnitude of the full-
scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between R
SET
and the full-scale output current on I
OUT
is given by I
OUT
(mA) = 7968 × V
REF
(V)/R
SET
(Ω).
Power Save Control Pin. The device is put into standby mode when PSAVE is low. The internal voltage reference
circuit is still active.
V
AA
PDOWN
DNC
CLOCK
15, 16
18
19
20
21
GND
I
OUT
I
OUT
COMP
V
REF
22
R
SET
23
PSAVE
Rev. A | Page 8 of 18
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