ADV7125
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
GND
G0
1
2
3
4
5
6
7
8
9
36 V
REF
35 COMP
PIN 1
INDICATOR
IOR
IOR
34
33
G1
G2
32 IOG
31 IOG
G3
ADV7125
TOP VIEW
G4
30 V
29 V
AA
AA
(Not to Scale)
G5
G6
28 IOB
27 IOB
26 GND
25 GND
G7 10
BLANK 11
SYNC 12
NOTES
1. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE
CONNECTED TO GND.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number
Mnemonic
Description
1, 2, 1ꢀ, 1ꢁ, 2ꢁ,
26, 39, ꢀ±
GND
Ground. All GND pins must be connected.
3 to 1±, 16 to
23, ꢀ1 to ꢀ8
G± to G7,
B± to B7,
R± to R7
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of
CLOCK. R±, G±, and B± are the least significant data bits. Unused pixel data inputs should be
connected to either the regular printed circuit board (PCB) power or ground plane.
11
BLANK
Composite Blank Control Input (TTL Compatible). A Logic ± on this control input drives the analog
outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of
CLOCK. While BLANK is a Logic ±, the R± to R7, G± to G7, and B± to B7 pixel inputs are ignored.
12
SYNC
Composite Sync Control Input (TTL Compatible). A Logic ± on the SYNC input switches off a
ꢀ± IRE current source. This is internally connected to the IOG analog output. SYNC does not override
any other control or data input; therefore, it should only be asserted during the blanking interval.
SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel,
the SYNC input should be tied to Logic ±.
13, 29, 3±
2ꢀ
VAA
CLOCK
Analog Power Supply (ꢁ V ± ꢁ%). All VAA pins on the ADV712ꢁ must be connected.
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R± to R7, G± to G7, B± to B7, SYNC,
and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK
should be driven by a dedicated TTL buffer.
33, 31, 27
3ꢀ, 32, 28
IOR, IOG, IOB
IOR, IOG, IOB
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-3ꢀ3A and RS-17± video levels into a doubly terminated 7ꢁ Ω
load. If the complementary outputs are not required, these outputs should be tied to ground.
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly
driving a doubly terminated 7ꢁ Ω coaxial cable. All three current outputs should have similar output
loads whether or not they are all being used.
3ꢁ
36
COMP
VREF
Compensation Pin. This is a compensation pin for the internal reference amplifier. A ±.1 μF ceramic
capacitor must be connected between COMP and VAA
.
Voltage Reference Input for DACs or Voltage Reference Output (1.23ꢁ V).
Rev. C | Page 8 of 16
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