ADV7125
CIRCUIT DESCRIPTION AND OPERATION
The ADV7125 contains three 8-bit DACs, with three input
channels, each containing an 8-bit register. Also integrated
on board the part is a reference amplifier. The CRT control
Table 7 details the resultant effect on the analog outputs of
BLANK SYNC
and
.
All these digital inputs are specified to accept TTL logic levels.
BLANK
functions,
ADV7125.
SYNC
and
, are integrated on board the
CLOCK INPUT
The CLOCK input of the ADV7125 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, is determined by the
on-screen resolution, according to the following equation:
DIGITAL INPUTS
There are 24 bits of pixel data (color information), R0 to R7,
G0 to G7, and B0 to B7, latched into the device on the rising
edge of each clock cycle. This data is presented to the three 8-bit
DACs and then converted to three analog (RGB) output wave-
forms (see Figure 4).
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh
Rate)/(Retrace Factor)
where:
CLOCK
Horiz Res is the number of pixels per line.
Vert Res is the number of lines per frame.
DIGITAL INPUTS
(R7 TO R0, G7 TO G0,
DATA
Refresh Rate is the horizontal scan rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system, or 30 Hz for an interlaced system.
Retrace Factor is the total blank time factor. This takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
B7 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG,
IOB, IOB)
Figure 4. Video Data Input/Output
The ADV7125 has two additional control signals that are latched
Therefore, for a graphics system with a 1024 × 1024 resolution,
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
BLANK
to the analog video outputs in a similar fashion.
and
are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
BLANK SYNC
SYNC
Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz. All video
data and control inputs are latched into the ADV7125 on the
rising edge of CLOCK, as previously described in the Digital
Inputs section. It is recommended that the CLOCK input to the
ADV7125 be driven by a TTL buffer (for example, the 74F244).
The
and
functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK
SYNC
and
digital inputs.
Figure 5 shows the analog output, RGB video waveform of the
SYNC
BLANK
on the analog
ADV7125. The influence of
and
video waveform is illustrated.
RED AND BLUE
GREEN
mA
V
mA
V
18.67
0.7
26.0
0.975
WHITE LEVEL
BLANK LEVEL
SYNC LEVEL
0
0
7.2
0.271
0
0
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. V = 1.235V, R = 530Ω.
REF SET
3. RS-343 LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 5. Typical RGB Video Output Waveform
Rev. C | Page 11 of 16
ADI [ ADI ]
