欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADV7125_11 参数 Datasheet PDF下载

ADV7125_11图片预览
型号: ADV7125_11
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz三通道,8位高速视频DAC [CMOS, 330 MHz Triple 8-Bit High Speed Video DAC]
分类和应用:
文件页数/大小: 16 页 / 293 K
品牌: AD [ ANALOG DEVICES ]
 浏览型号ADV7125_11的Datasheet PDF文件第1页浏览型号ADV7125_11的Datasheet PDF文件第2页浏览型号ADV7125_11的Datasheet PDF文件第3页浏览型号ADV7125_11的Datasheet PDF文件第4页浏览型号ADV7125_11的Datasheet PDF文件第6页浏览型号ADV7125_11的Datasheet PDF文件第7页浏览型号ADV7125_11的Datasheet PDF文件第8页浏览型号ADV7125_11的Datasheet PDF文件第9页  
ADV7125
5 V TIMING SPECIFICATIONS
V
AA
= 5 V ± 5%,
V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
,
2
unless otherwise noted, T
J MAX
= 110°C.
Table 3.
Parameter
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Transition Time
Analog Output Skew
CLOCK CONTROL
CLOCK Frequency
7
Symbol
t
6
t
7
t
8
9
f
CLK
0.5
0.5
0.5
0.5
1.5
4.17
1.875
1.875
2.85
2.85
8.0
8.0
1.0
Min
Typ
5.5
1.0
15
Max
Unit
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
50 MHz grade
140 MHz grade
240 MHz grade
Conditions
2
50
140
240
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay
PSAVE Up Time
6
1
2
t
1
t
2
t
3
t
4
t
5
t
4
t
5
t
4
t
5
t
PD
t
10
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 50 MHz
f
CLK_MAX
= 50 MHz
1.0
2
1.0
10
The maximum and minimum specifications are guaranteed over this range.
Temperature range T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Rev. C | Page 5 of 16