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ADV7123KSTZ50 参数 Datasheet PDF下载

ADV7123KSTZ50图片预览
型号: ADV7123KSTZ50
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz的三路10位高速视频DAC [CMOS, 330 MHz Triple 10-Bit High Speed Video DAC]
分类和应用: 转换器数模转换器PC
文件页数/大小: 24 页 / 340 K
品牌: ADI [ ADI ]
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ADV7123  
Table 9. Typical Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)  
IOG (mA)  
IOR/IOB (mA)  
SYNC  
BLANK  
Video Output Level  
White Level  
Video  
Video to BLANK  
Black Level  
Black to BLANK  
BLANK Level  
SYNC Level  
IOG (mA)  
IOR/IOB (mA)  
DAC Input Data  
0x3FFH  
Data  
26.0  
Video + 7.2  
Video  
7.2  
0
0
18.67  
Video  
Video  
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
18.67 − Video  
18.67 − Video  
18.67  
18.67 − Video  
18.67 − Video  
18.67  
Data  
0
0
0
0
0x000H  
0x000H  
18.67  
18.67  
7.2  
0
18.67  
18.67  
0xXXXH (don’t care)  
0xXXXH (don’t care)  
18.67  
18.67  
sources in a monolithic design guarantees monotonicity and  
low glitch. The on-board operational amplifier stabilizes the  
full-scale output current against temperature and power supply  
variations.  
VIDEO SYNCHRONIZATION AND CONTROL  
SYNC  
The ADV7123 has a single composite sync (  
) input  
control. Many graphics processors and CRT controllers have the  
ability of generating horizontal sync (HSYNC), vertical sync  
ANALOG OUTPUTS  
SYNC  
(VSYNC), and composite  
In a graphics system that does not automatically generate a  
SYNC  
.
The ADV7123 has three analog outputs, corresponding to the  
red, green, and blue video signals.  
composite  
signal, the inclusion of some additional logic  
SYNC  
circuitry enables the generation of a composite  
signal.  
The red, green, and blue analog outputs of the ADV7123 are  
high impedance current sources. Each one of these three RGB  
current outputs is capable of directly driving a 37.5 ꢁ load, such  
as a doubly terminated 75 ꢁ coaxial cable. Figure 24 shows  
the required configuration for each of the three RGB outputs  
connected into a doubly terminated 75 ꢁ load. This arrangement  
develops RS-343A video output voltage levels across a 75 ꢁ  
monitor.  
The sync current is internally connected directly to the IOG  
output, thus encoding video synchronization information onto  
the green video channel. If it is not required to encode sync  
information onto the ADV7123, the  
to logic low.  
SYNC  
input should be tied  
REFERENCE INPUT  
The ADV7123 contains an on-board voltage reference. The VREF  
pin is normally terminated to VAA through a 0.1 μF capacitor.  
Alternatively, the part can, if required, be overdriven by an  
external 1.23 V reference (AD1580).  
A suggested method of driving RS-170 video levels into a 75 ꢁ  
monitor is shown in Figure 25. The output current levels of the  
DACs remain unchanged, but the source termination resistance,  
ZS, on each of the three DACs is increased from 75 ꢁ to 150 ꢁ.  
IOR, IOG, IOB  
A resistance, RSET, connected between the RSET pin and GND,  
determines the amplitude of the output video level according to  
Equation 1 and Equation 2 for the ADV7123.  
Z
= 75  
0
DACs  
(CABLE)  
Z
= 75Ω  
S
Z
= 75Ω  
L
(SOURCE  
TERMINATION)  
IOG (mA) = 11,445 × VREF (V)/RSET (Ω)  
(1)  
(2)  
(MONITOR)  
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)  
SYNC  
TERMINATION REPEATED THREE TIMES  
FOR RED, GREEN, AND BLUE DACs  
Equation 1 applies to the ADV7123 only, when  
is being  
is not being encoded onto the green channel,  
Equation 1 is similar to Equation 2.  
SYNC  
used. If  
Figure 24. Analog Output Termination for RS-343A  
IOR, IOG, IOB  
Z
= 75Ω  
0
Using a variable value of RSET allows for accurate adjustment of  
the analog output video levels. Use of a fixed 560 ꢁ RSET resistor  
yields the analog output levels quoted in the Specifications section.  
These values typically correspond to the RS-343A video wave-  
form values, as shown in Figure 23.  
DACs  
Z
(SOURCE  
TERMINATION)  
(CABLE)  
= 150Ω  
S
Z
= 75Ω  
L
(MONITOR)  
TERMINATION REPEATED THREE TIMES  
FOR RED, GREEN, AND BLUE DACs  
DACs  
The ADV7123 contains three matched 10-bit DACs. The DACs  
are designed using an advanced, high speed, segmented architec-  
ture. The bit currents corresponding to each digital input are  
routed to either the analog output (bit = 1) or GND (bit = 0)  
by a sophisticated decoding scheme. Because all this circuitry is  
on one monolithic device, matching between the three DACs is  
optimized. As well as matching, the use of identical current  
Figure 25. Analog Output Termination for RS-170  
More detailed information regarding load terminations for  
various output configurations, including RS-343A and RS-170,  
is available in the AN-205 Application Note, Video Formats and  
Required Load Terminations, available from Analog Devices, at  
www.analog.com.  
Rev. D | Page 18 of 24  
 
 
 
 
 
 
 
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