ADuM1300/ADuM1301
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM130x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
between Pins 1 and 2 for V
DD1
and between Pins 15 and 16 for
V
DD2
. The capacitor value should be between 0.01 µF and 0.1 µF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypass-
ing between Pins 1 and 8 and between Pins 9 and 16 should also
be considered unless the ground pair on each package side is
connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC/OC
NC
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/IC
NC
V
E2
GND
2
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the trans-
former. The decoder is bistable and is therefore either set or
reset by the pulses, indicating input logic transitions. In the
absence of logic transitions of more than 2 µs at the input, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than about 5 µs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 10)
by the watchdog timer circuit.
The ADuM130x is extremely immune to external magnetic
fields. The limitation on the ADuM130x’s magnetic field
immunity is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this may occur. The 3 V operating
condition of the ADuM130x is examined because it represents
the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V
= (–dβ/dt)
∑
∏r
n2
;
n
= 1, 2,…,
N
where:
β is magnetic flux density (gauss).
N
is the number of turns in the receiving coil.
r
n
is the radius of the n
th
turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM130x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isola-
tion barrier is minimized. Furthermore, the board layout should
be designed such that any coupling that does occur equally
affects all pins on a given component side. Failure to ensure this
could cause voltage differentials between pins exceeding the
device’s Absolute Maximum Ratings, thereby leading to latch-up
or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propaga-
tion delay to a logic low output may differ from the propagation
delay to a logic high.
INPUT (V
IX
)
50%
OUTPUT (V
OX
)
50%
Figure 15. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM130x component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM130x
components operating under the same conditions.
Rev. C | Page 16 of 20
03787-0-016
t
PLH
t
PHL
03787-0-015
AD [ ANALOG DEVICES ]
