ADuM1200/ADuM1201
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
25 Mbps (CR Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (25)
6.3
3.4
8.0
4.8
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (25)
3.4
6.3
4.8
8.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
VIH
VIL
−10
0.7 VDD1, VDD2
0.01
10
µA
V
V
V
V
0 ≤ VIA, VIB ≤ VDD1 or VDD2
Logic High Input Threshold
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
0.3 VDD1, VDD2
0.8
0.4
VOAH
VOBH
,
VDD1
VDD2 − 0.1
VDD1
DD2 − 0.5
,
VDD1
,
V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
VDD2
,
VDD1
,
V
V
VDD2 − 0.2
Logic Low Output Voltages
VOAL, VOBL
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
Mbps
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay4
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
tR/tF
150
40
50
4
Pulse-Width Distortion, |tPLH − tPHL
Propagation Delay Skew5
Channel-to-Channel Matching6
Output Rise/Fall Time (10% to 90%)
ADuM120xBR
|
50
ns
ns
10
Minimum Pulse Width2
Maximum Data Rate3
PW
100
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
15
Propagation Delay4
tPHL, tPLH
PWD
55
3
4
Pulse-Width Distortion, |tPLH − tPHL
Change Versus Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
5
tPSK
tPSKCD
22
3
ns
Channel-to-Channel Matching,
tPSKOD
tR/tf
22
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3.0
2.5
ns
ns
3 V/5 V Operation
Rev. B | Page 8 of 20
ADI [ ADI ]
