ADuM1200/ADuM1201
Parameter
25 Mbps (CR Grade Only)
V
DD1
Supply Current
5 V/3 V Operation
3 V/5 V Operation
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Symbol
I
DD1 (25)
6.3
3.4
I
DD2 (25)
3.4
6.3
I
IA
, I
IB
V
IH
V
IL
−10
0.7 V
DD1
, V
DD2
0.8
0.4
V
DD1
,
V
DD2
− 0.1
V
DD1
,
V
DD2
− 0.5
0.01
4.8
8.0
10
0.3 V
DD1
, V
DD2
mA
mA
µA
V
V
V
V
V
V
0.1
0.1
0.4
V
V
V
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
0 ≤ V
IA
, V
IB
≤ V
DD1
or V
DD2
8.0
4.8
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
Min
Typ
Max
Unit
Test Conditions
V
OAH
,
V
OBH
Logic Low Output Voltages
V
OAL
, V
OBL
V
DD1
,
V
DD2
V
DD1
,
V
DD2
− 0.2
0.0
0.04
0.2
I
Ox
= −20 µA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxL
I
Ox
= 400 µA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM120xAR
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
PLH
− t
PHL
Propagation Delay Skew
Channel-to-Channel Matching
Output Rise/Fall Time (10% to 90%)
ADuM120xBR
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
PLH
− t
PHL
Change Versus Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
t
R
/t
F
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
t
R
/t
f
3.0
2.5
10
15
5
1
50
1000
150
40
50
50
10
100
55
3
22
3
22
ns
Mbps
ns
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
ns
ns
Rev. B | Page 8 of 20
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