ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
MCU CLOCK RATE
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
Using an External Clock
326
41.78
kHz
CD12 = 7
MHz
MHz
MHz
CD12 = 0
0.05
0.05
44
41.78
TA = 85°C
TA = 125°C
START-UP TIME
Core clock = 41.78 MHz
At Power-On
From Pause/Nap Mode
130
24
3.06
1.58
1.7
ms
ns
µs
ms
ms
CD12 = 0
CD12 = 7
From Sleep Mode
From Stop Mode
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
Element Propagation Delay
POWER REQUIREMENTS13, 14
Power Supply Voltage Range
12
2.5
ns
ns
From input pin to output pin
AVDD to AGND and IOVDD to IOGND 2.7
Analog Power Supply Currents
AVDD Current
3.6
25
V
200
400
3
µA
µA
µA
ADC in idle mode; all parts except ADuC7019
ADC in idle mode; ADuC7019 only
DACVDD Current15
Digital Power Supply Current
IOVDD Current in Normal Mode
Code executing from Flash/EE
CD12 = 7
7
10
15
45
30
400
1000
mA
mA
mA
mA
µA
11
40
25
250
600
CD12 = 3
CD12 = 0 (41.78 MHz clock)
CD12 = 0 (41.78 MHz clock)
TA = 85°C
IOVDD Current in Pause Mode
IOVDD Current in Sleep Mode
µA
TA = 125°C
Additional Power Supply Currents
ADC
2
0.7
700
mA
mA
µA
@ 1 MSPS
@ 62.5 kSPS
per DAC
DAC
ESD TESTS
2.5 V reference, TA = 25°C
HBM Passed Up To
FCIDM Passed Up To
4
0.5
kV
kV
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Apply to all ADC input channels.
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 59. Based on external ADC
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 DAC linearity is calculated using a reduced code range of 100 to 3995.
8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF
.
9 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
11 Test carried out with a maximum of eight I/Os set to a low output level.
12 See the POWCON register.
13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
14 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
15 On the ADuC7019/20/21/22, this current must be added to the AVDD current.
Rev. F | Page 12 of 104
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