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ADuC7020BCPZ62I 参数 Datasheet PDF下载

ADuC7020BCPZ62I图片预览
型号: ADuC7020BCPZ62I
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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ADuC7019/20/21/22/24/25/26/27/28/29  
SPECIFICATIONS  
Data Sheet  
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted.  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
ADC CHANNEL SPECIFICATIONS  
ADC Power-Up Time  
DC Accuracy1, 2  
Eight acquisition clocks and fADC/2  
5
μs  
Resolution  
Integral Nonlinearity  
12  
Bits  
LSB  
LSB  
LSB  
LSB  
LSB  
0.6  
1.0  
0.5  
+0.7/−0.6  
1
1.5  
2.5 V internal reference  
1.0 V external reference  
2.5 V internal reference  
1.0 V external reference  
ADC input is a dc voltage  
Differential Nonlinearity3, 4  
+1/−0.9  
DC Code Distribution  
ENDPOINT ERRORS5  
Offset Error  
Offset Error Match  
Gain Error  
1
1
2
1
2
5
LSB  
LSB  
LSB  
LSB  
Gain Error Match  
DYNAMIC PERFORMANCE  
Signal-to-Noise Ratio (SNR)  
Total Harmonic Distortion (THD)  
Peak Harmonic or Spurious Noise  
(PHSN)  
fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS  
Includes distortion and noise components  
69  
−78  
−75  
dB  
dB  
dB  
Channel-to-Channel Crosstalk  
ANALOG INPUT  
−80  
dB  
Measured on adjacent channels  
Input Voltage Ranges  
Differential Mode  
6
VCM VREF/2  
V
Single-Ended Mode  
Leakage Current  
Input Capacitance  
0 to VREF  
6
V
µA  
pF  
1
20  
During ADC acquisition  
ON-CHIP VOLTAGE REFERENCE  
Output Voltage  
0.47 µF from VREF to AGND  
2.5  
V
Accuracy  
5
mV  
ppm/°C  
dB  
ms  
TA = 25°C  
TA = 25°C  
Reference Temperature Coefficient  
Power Supply Rejection Ratio  
Output Impedance  
Internal VREF Power-On Time  
EXTERNAL REFERENCE INPUT  
Input Voltage Range  
DAC CHANNEL SPECIFICATIONS  
DC Accuracy7  
40  
75  
70  
1
0.625  
AVDD  
V
RL = 5 kΩ, CL = 100 pF  
Resolution  
Relative Accuracy  
Differential Nonlinearity  
Offset Error  
Gain Error8  
12  
2
Bits  
LSB  
LSB  
mV  
%
1
15  
1
Guaranteed monotonic  
2.5 V internal reference  
Gain Error Mismatch  
ANALOG OUTPUTS  
0.1  
%
% of full scale on DAC0  
Output Voltage Range_0  
Output Voltage Range_1  
Output Voltage Range_2  
Output Impedance  
0 to DACREF  
0 to 2.5  
0 to DACVDD  
2
V
V
V
DACREF range: DACGND to DACVDD  
Rev. F | Page 10 of 104