ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Master Timing
and
describe SPI port master operations.
Table 27. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
t
HSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
t
SDSCIM
SPISELx Low to First SCK edge (x=0 or 1)
t
SPICHM
Serial Clock High period
t
SPICLM
Serial Clock Low period
t
SPICLK
Serial Clock Period
t
HDSM
Last SCK Edge to SPISELx High (x=0 or 1)
Sequential Transfer Delay
t
SPITDM
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
Min
7.5
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
0
–1.0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
4.0
SPISELx
(OUTPUT)
t
SDSCIM
SCK
(CPOL = 0)
(OUTPUT)
t
SPICHM
t
SPICLM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
SCK
(CPOL = 1)
(OUTPUT)
t
SPICHM
t
DDSPIDM
MOSI
(OUTPUT)
CPHA=1
MISO
(INPUT)
MSB
t
HDSPIDM
LSB
t
SSPIDM
MSB VALID
t
HSPIDM
t
SSPIDM
LSB VALID
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
CPHA=0
MISO
(INPUT)
MSB
t
HDSPIDM
LSB
t
SSPIDM
MSB VALID
t
HSPIDM
LSB VALID
Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. 0 |
Page 33 of 56 | March 2004
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