SPECIFICATIONS
Component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
V
DDINT
Internal Supply Voltage
1
V
DDINT
Internal Supply Voltage
V
DDINT
Internal Supply Voltage
V
DDINT
Internal Supply Voltage
V
DDINT
Internal Supply Voltage
V
DDEXT
External Supply Voltage
3
V
DDEXT
External Supply Voltage
V
DDRTC
Real-Time Clock
Power Supply Voltage
V
DDRTC
Real-Time Clock
Power Supply Voltage
V
IH
V
IH
V
IL
V
IL
T
J
T
J
T
J
T
J
T
J
T
J
1
2
Conditions
Nonautomotive 400 MHz and 500 MHz speed grade models
2
Nonautomotive 533 MHz speed grade models
600 MHz speed grade models
Automotive 400 MHz speed grade models
Automotive 533 MHz speed grade models
Nonautomotive grade models
Automotive grade models
Nonautomotive grade models
Automotive grade models
V
DDEXT
=1.85 V
V
DDEXT
=Maximum
V
DDEXT
=Maximum
V
DDEXT
=1.75 V
V
DDEXT
=2.7 V
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ T
AMBIENT
= 0°C to +70°C
Min Nominal
0.8 1.2
0.8 1.25
0.8 1.30
0.95 1.2
0.95 1.25
1.75 1.8/3.3
2.7 3.3
1.75 1.8/3.3
2.7 3.3
1.3
2.0
2.2
Max Unit
1.45
1.45
1.45
1.45
1.45
3.6
3.6
3.6
3.6
V
V
V
V
V
V
V
V
V
V
V
V
+0.3 V
+0.6 V
High Level Input Voltage
4, 5
High Level Input Voltage
Low Level Input Voltage
7
Low Level Input Voltage
Junction Temperature
Junction Temperature
Junction Temperature
Junction Temperature
Junction Temperature
Junction Temperature
V
IHCLKIN
High Level Input Voltage
6
0
+95
°C
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ T
AMBIENT
= –40°C to +85°C –40
160-Ball Chip Scale Ball Grid Array (CSP_BGA) @ T
AMBIENT
= –40°C to +105°C –40
169-Ball Plastic Ball Grid Array (PBGA) @ T
AMBIENT
= –40°C to +105°C
169-Ball Plastic Ball Grid Array (PBGA) @ T
AMBIENT
= –40°C to +85°C
176-Lead Quad Flatpack (LQFP) @ T
AMBIENT
= –40°C to +85°C
–40
–40
–40
+105 °C
+125 °C
+125 °C
+105 °C
+100 °C
The regulator can generate V
DDINT
at levels of 0.85 V to 1.2 V with –5% to +10% tolerance, 1.25 V with –4% to +10% tolerance, and 1.3 V with –0% to +10% tolerance.
See
3
When V
DDEXT
< 2.25 V, on-chip voltage regulation is not supported.
4
Applies to all input and bidirectional pins except CLKIN.
5
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are 3.3 V tolerant (always accepts up to 3.6 V maximum V
IH
), but voltage compliance (on outputs, V
OH
) depends on
the input V
DDEXT
, because V
OH
(maximum) approximately equals V
DDEXT
(maximum). This 3.3 V tolerance applies to bidirectional pins (DATA15–0, TMR2–0, PF15–0, PPI3–0,
RSCLK1–0, TSCLK1–0, RFS1–0, TFS1–0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS,
TRST, CLKIN, RESET, NMI, and BMODE1–0).
6
Applies to CLKIN pin only.
7
Applies to all input and bidirectional pins.
Rev. I
|
Page 20 of 64 |
August 2013
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