ADSP-BF531/ADSP-BF532
Additionally, DMA transfers can be accomplished between any
of the DMA-capable peripherals and external devices connected
to the external memory interfaces, including the SDRAM
controller and the asynchronous memory controller. DMA-
capable peripherals include the SPORTs, SPI port, UART, and
PPI. Each individual DMA-capable peripheral has at least one
dedicated DMA channel.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
The ADSP-BF531/ADSP-BF532 processor DMA controller
supports both 1-dimensional (1-D) and 2-dimensional (2-D)
DMA transfers. DMA transfer initialization can be imple-
mented from registers or from sets of parameters called
descriptor blocks.
Like other peripherals, the RTC can wake up the processor from
sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from a powered-down state.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to 32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 5.
RTXI
RTXO
R1
X1
Examples of DMA types supported by the ADSP-BF531/
ADSP-BF532 processor DMA controller include:
• A single, linear buffer that stops upon completion
C1
C2
• A circular, autorefreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
SUGGESTED COMPONENTS:
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 MΩ
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the ADSP-BF531/ADSP-BF532 processor
system. This enables transfers of blocks of data between any of
the memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor-
based methodology or by a standard register-based autobuffer
mechanism.
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
Figure 5. External Components for RTC
WATCHDOG TIMER
The ADSP-BF531/ADSP-BF532 processor includes a 32-bit
timer that can be used to implement a software watchdog func-
tion. A software watchdog can improve system availability by
forcing the processor to a known state through generation of a
hardware reset, nonmaskable interrupt (NMI), or general-pur-
pose interrupt, if the timer expires before being reset by
software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
REAL-TIME CLOCK
The ADSP-BF531/ADSP-BF532 processor real-time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
32.768 kHz crystal external to the ADSP-BF531/ADSP-BF532
processor. The RTC peripheral has dedicated power supply pins
so that it can remain powered up and clocked even when the
rest of the processor is in a low power state. The RTC provides
several programmable interrupt options, including interrupt
per second, minute, hour, or day clock ticks, interrupt on pro-
grammable stopwatch countdown, or interrupt at a
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF531/ADSP-BF532 proces-
sor peripherals. After a reset, software can determine if the
watchdog was the source of the hardware reset by interrogating
a status bit in the watchdog timer control register.
programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a 24
hour counter, and a 32,768 day counter.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK
.
Rev. D
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Page 9 of 60
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August 2006
ADI [ ADI ]
