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ADSP-BF532WBSTZ-4A 参数 Datasheet PDF下载

ADSP-BF532WBSTZ-4A图片预览
型号: ADSP-BF532WBSTZ-4A
PDF下载: 下载PDF文件 查看货源
内容描述: Blackfin嵌入式处理器 [Blackfin Embedded Processor]
分类和应用:
文件页数/大小: 60 页 / 3025 K
品牌: ADI [ ADI ]
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ADSP-BF531/ADSP-BF532  
These modes support ADC/DAC connections, as well as video  
communication with hardware signaling. Many of the modes  
support more than one level of frame synchronization. If  
desired, a programmable delay can be inserted between asser-  
tion of a frame sync and reception/transmission of data.  
Hibernate Operating Mode—Maximum Static Power  
Savings  
The hibernate mode maximizes static power savings by dis-  
abling the voltage and clocks to the processor core (CCLK) and  
to all the synchronous peripherals (SCLK). The internal voltage  
regulator for the processor can be shut off by writing b#00 to  
the FREQ bits of the VR_CTL register. This disables both CCLK  
and SCLK. Furthermore, it sets the internal power supply volt-  
age (VDDINT) to 0 V to provide the lowest static power dissipation.  
Any critical information stored internally (memory contents,  
register contents, etc.) must be written to a nonvolatile storage  
device prior to removing power if the processor state is to be  
preserved. Since VDDEXT is still supplied in this mode, all of the  
external pins three-state, unless otherwise specified. This allows  
other devices that may be connected to the processor to have  
power still applied without drawing unwanted current. The  
internal supply regulator can be woken up either by a real-time  
clock wakeup or by asserting the RESET pin.  
DYNAMIC POWER MANAGEMENT  
The ADSP-BF531/ADSP-BF532 processor provides five operat-  
ing modes, each with a different performance/power profile. In  
addition, dynamic power management provides the control  
functions to dynamically alter the processor core supply voltage,  
further reducing power dissipation. Control of clocking to each  
of the ADSP-BF531/ADSP-BF532 processor peripherals also  
reduces power consumption. See Table 5 for a summary of the  
power settings for each mode.  
Table 4. Power Domains  
Power Domain  
VDD Range  
VDDINT  
All internal logic, except RTC  
RTC internal logic and crystal I/O  
All other I/O  
Sleep Operating Mode—High Dynamic Power Savings  
VDDRTC  
The sleep mode reduces dynamic power dissipation by disabling  
the clock to the processor core (CCLK). The PLL and system  
clock (SCLK), however, continue to operate in this mode. Typi-  
cally an external event or RTC activity will wake up the  
processor. When in the sleep mode, assertion of wakeup will  
cause the processor to sense the value of the BYPASS bit in the  
PLL control register (PLL_CTL). If BYPASS is disabled, the pro-  
cessor will transition to the full-on mode. If BYPASS is enabled,  
the processor will transition to the active mode.  
VDDEXT  
Full-On Operating Mode—Maximum Performance  
In the full-on mode, the PLL is enabled and is not bypassed,  
providing capability for maximum operational frequency. This  
is the power-up default execution state in which maximum per-  
formance can be achieved. The processor core and all enabled  
peripherals run at full speed.  
When in the sleep mode, system DMA access to L1 memory is  
not supported.  
Active Operating Mode—Moderate Power Savings  
In the active mode, the PLL is enabled but bypassed. Because the  
PLL is bypassed, the processor’s core clock (CCLK) and system  
clock (SCLK) run at the input clock (CLKIN) frequency. In this  
mode, the CLKIN to CCLK multiplier ratio can be changed,  
although the changes are not realized until the full-on mode is  
entered. DMA access is available to appropriately configured L1  
memories.  
Deep Sleep Operating Mode—Maximum Dynamic Power  
Savings  
The deep sleep mode maximizes dynamic power savings by dis-  
abling the clocks to the processor core (CCLK) and to all  
synchronous peripherals (SCLK). Asynchronous peripherals,  
such as the RTC, may still be running but will not be able to  
access internal resources or external memory. This powered-  
down mode can only be exited by assertion of the reset interrupt  
(RESET) or by an asynchronous interrupt generated by the  
RTC. When in deep sleep mode, an RTC asynchronous inter-  
rupt causes the processor to transition to the active mode.  
Assertion of RESET while in deep sleep mode causes the proces-  
sor to transition to the full-on mode.  
In the active mode, it is possible to disable the PLL through the  
PLL control register (PLL_CTL). If disabled, the PLL must be  
re-enabled before transitioning to the full-on or sleep modes.  
Table 5. Power Settings  
Core  
Clock  
System  
Clock  
PLL  
Core  
Power Savings  
Mode  
Full-On  
Active  
PLL  
Bypassed (CCLK) (SCLK)  
Power  
As shown in Table 4, the ADSP-BF531/ADSP-BF532 processor  
supports three different power domains. The use of multiple  
power domains maximizes flexibility, while maintaining com-  
pliance with industry standards and conventions. By isolating  
the internal logic of the ADSP-BF531/ADSP-BF532 processor  
into its own power domain, separate from the RTC and other  
I/O, the processor can take advantage of dynamic power man-  
agement, without affecting the RTC or other I/O devices. There  
are no sequencing requirements for the various power domains.  
Enabled No  
Enabled Enabled On  
Enabled/ Yes  
Disabled  
Enabled Enabled On  
Sleep  
Enabled  
Disabled Enabled On  
Disabled Disabled On  
Disabled Disabled Off  
Deep Sleep Disabled  
Hibernate Disabled  
Rev. D  
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Page 12 of 60  
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August 2006