ADSP-BF531/ADSP-BF532/ADSP-BF533
frequency. The capacitor and resistor values shown in
are typical values only. The capacitor values are dependent upon
the crystal manufacturer's load capacitance recommendations
and the physical PCB layout. The resistor value depends on the
drive level specified by the crystal manufacturer. System designs
should verify the customized values based on careful investiga
tion on multiple devices over the allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in
As shown in
the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 0.5× to 64× multiplica
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly
frequency changes can be effected by simply writing to the
PLL_DIV register.
“FI NE” ADJUSTMENT
REQUI RES PLL SEQ UENCING
“CO ARSE” ADJUSTMENT
ON-THE-FLY
to the PLL divisor register (PLL_DIV). When the SSEL value is
changed, it will affect all the peripherals that derive their clock
signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Example Frequency Ratios
Divider Ratio (MHz)
VCO/CCLK
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
400
100
8:1
200
25
Signal Name
CSEL1–0
00
01
10
11
BOOTING MODES
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has
two mechanisms (listed in
for automatically loading
internal L1 instruction memory after a reset. A third mode is
provided to execute from external memory, bypassing the boot
sequence.
Table 8. Booting Modes
÷ 1, 2, 4,
8
CLKIN
PLL
0.5× to 64×
CCLK
VCO
÷ 1 to 15
SCLK
BMODE1–0
00
01
10
11
SCLK
≤
CCLK
SCLK
≤
133 MHz
Figure 9. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
illustrates typical system clock ratios.
Table 6. Example System Clock Ratios
Example Frequency Ratios
Divider Ratio (MHz)
VCO/SCLK
VCO
SCLK
1:1
100
100
3:1
400
133
10:1
500
50
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit FLASH
Boot from serial master connected to SPI
Boot from serial slave EEPROM /flash (8-,16-,
or 24-bit address range, or Atmel AT45DB041,
AT45DB081, or AT45DB161serial flash)
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple
ment the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit or 16-bit external flash memory – The flash
boot routine located in boot ROM memory space is set up
using asynchronous Memory Bank 0. All configuration set
tings are set for the slowest device possible (3-cycle hold
time; 15-cycle R/W access times; 4-cycle setup).
• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit
addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) – The SPI uses the PF2 output pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-, or
Signal Name
SSEL3–0
0001
0011
1010
The maximum frequency of the system clock is f
SCLK
. The divisor
ratio must be chosen to limit the system clock frequency to its
maximum of f
SCLK
. The SSEL value can be changed dynamically
without any PLL lock latencies by writing the appropriate values
Rev. E |
Page 14 of 60 |
July 2007
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