ADSP-BF531/ADSP-BF532/ADSP-BF533
24-bit addressable EEPROM/flash device is detected, and
begins clocking data into the processor at the beginning of
L1 instruction memory.
• Boot from SPI serial master – The Blackfin processor oper
ates in SPI slave mode and is configured to receive the bytes
of the LDR file from an SPI host (master) agent. To hold off
the host device from transmitting while the boot ROM is
busy, the Blackfin processor asserts a GPIO pin, called host
wait (HWAIT), to signal the host device not to send any
more bytes until the flag is deasserted. The GPIO pin is
chosen by the user and this information is transferred to
the Blackfin processor via bits[10:5] of the FLAG header in
the LDR image.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
DEVELOPMENT TOOLS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor is sup
ported by a complete set of CROSSCORE
®†
software and
hardware development tools, including Analog Devices emula
tors and VisualDSP++
®‡
development environment. The same
emulator hardware that supports other Blackfin processors also
fully emulates the ADSP-BF531/ADSP-BF532/ADSP-BF533
processor.
The VisualDSP++ project management environment lets pro
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The processor
has architectural features that improve the efficiency of com
piled C/C++ code.
The VisualDSP++ debugger has a number of important fea
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity.
Statistical profiling enables the programmer to nonintrusively
poll the processor as it is running the program. This feature,
unique to VisualDSP++, enables the software developer to pas
sively gather important code execution metrics without
interrupting the real-time characteristics of the program. Essen
tially, the developer can identify bottlenecks in software quickly
and efficiently. By using the profiler, the programmer can focus
on those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information).
• Insert breakpoints.
• Set conditional breakpoints on registers, memory,
and stacks.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/CPU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program
ming model.
†
‡
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
Rev. E |
Page 15 of 60 |
July 2007
AD [ ANALOG DEVICES ]
