ADSP-BF531/ADSP-BF532/ADSP-BF533
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces
sor to transition to the full-on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu
lator for the processor can be shut off by writing b#00 to
the FREQ bits of the VR_CTL register. In addition to disabling
the clocks, this sets the internal power supply voltage (V
DDINT
) to
0 V to provide the lowest static power dissipation. Any critical
information stored internally (memory contents, register con
tents, etc.) must be written to a nonvolatile storage device prior
to removing power if the processor state is to be preserved.
Since V
DDEXT
is still supplied in this mode, all of the external pins
three-state, unless otherwise specified. This allows other devices
that may be connected to the processor to still have power
applied without drawing unwanted current. The internal supply
regulator can be woken up either by a real-time clock wakeup or
by asserting the RESET pin.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Table 4. Power Settings
Core
PLL
Clock
Mode
PLL
Bypassed (CCLK)
Full-On
Enabled No
Enabled
Active
Enabled/ Yes
Enabled
Disabled
Sleep
Enabled
Disabled
Deep Sleep Disabled
Disabled
Hibernate Disabled
Disabled
System
Clock
Core
(SCLK)
Power
Enabled On
Enabled On
Enabled On
Disabled On
Disabled Off
Power Savings
As shown in
the ADSP-BF531/ADSP-BF532/
ADSP-BF533 processor supports three different power
domains. The use of multiple power domains maximizes flexi
bility, while maintaining compliance with industry standards
and conventions. By isolating the internal logic of the processor
into its own power domain, separate from the RTC and other
I/O, the processor can take advantage of dynamic power man
agement without affecting the RTC or other I/O devices. There
are no sequencing requirements for the various power domains.
Table 5. Power Domains
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
V
DD
Range
V
DDINT
V
DDRTC
V
DDEXT
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi
cally an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL control register (PLL_CTL). If BYPASS is disabled, the pro
cessor will transition to the full-on mode. If BYPASS is enabled,
the processor will transition to the active mode.
When in the sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the ADSP-BF531/
ADSP-BF532/ADSP-BF533 processor allows both the proces
sor’s input voltage (V
DDINT
) and clock frequency (f
CCLK
) to be
dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
Rev. E |
Page 12 of 60 |
July 2007
AD [ ANALOG DEVICES ]
