ADSP-BF531/ADSP-BF532
GENERAL DESCRIPTION
The ADSP-BF531/ADSP-BF532 processors are members of the
Blackfin family of products, incorporating the Analog Devices/
Intel Micro Signal Architecture (MSA). Blackfin processors
combine a dual-MAC state-of-the-art signal processing engine,
the advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single instruction, multiple data (SIMD)
multimedia capabilities into a single instruction set architecture.
ADSP-BF531/ADSP-BF532 PROCESSOR
PERIPHERALS
The ADSP-BF531/ADSP-BF532 processor contains a rich set of
peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see the functional block
diagram in Figure 1 on Page 1). The general-purpose peripher-
als include functions such as UART, timers with PWM (pulse-
width modulation) and pulse measurement capability, general-
purpose flag I/O pins, a real-time clock, and a watchdog timer.
This set of functions satisfies a wide variety of typical system
support needs and is augmented by the system expansion capa-
bilities of the part. In addition to these general-purpose
The Blackfin processors are completely code and pin compati-
ble, differing only with respect to their performance and on-
chip memory. Specific performance and memory configura-
tions are shown in Table 1.
Table 1. Processor Comparison
peripherals, the ADSP-BF531/ADSP-BF532 processor contains
high speed serial and parallel ports for interfacing to a variety of
audio, video, and modem codec functions; an interrupt control-
ler for flexible management of interrupts from the on-chip
peripherals or external sources; and power management control
functions to tailor the performance and power characteristics of
the processor and system to many application scenarios.
ADSP-BF531
ADSP-BF532
Maximum Performance 400 MHz 800 MMACs 400 MHz 800 MMACs
Instruction
SRAM/Cache
16K bytes
16K bytes
Instruction SRAM
16K bytes
16K bytes
32K bytes
32K bytes
Data
SRAM/Cache
All of the peripherals, except for general-purpose I/O, real-time
clock, and timers, are supported by a flexible DMA structure.
There is also a separate memory DMA channel dedicated to
data transfers between the processor’s various memory spaces,
including external SDRAM and asynchronous memory. Multi-
ple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activ-
ity on all of the on-chip and external peripherals.
Scratchpad
4K bytes
4K bytes
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
The ADSP-BF531/ADSP-BF532 processor includes an on-chip
voltage regulator in support of the ADSP-BF531/ADSP-BF532
processor dynamic power management capability. The voltage
regulator provides a range of core voltage levels from a single
2.25 V to 3.6 V input. The voltage regulator can be bypassed at
the user’s discretion.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
dynamic power management—the ability to vary both the volt-
age and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, com-
pared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 6, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the
register file.
SYSTEM INTEGRATION
The ADSP-BF531/ADSP-BF532 processors are highly inte-
grated system-on-a-chip solutions for the next generation of
digital communication and consumer multimedia applications.
By combining industry-standard interfaces with a high perfor-
mance signal processing core, users can develop cost-effective
solutions quickly without the need for costly external compo-
nents. The system peripherals include a UART port, an SPI port,
two serial ports (SPORTs), four general-purpose timers (three
with PWM capability), a real-time clock, a watchdog timer, and
a parallel peripheral interface.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and
Rev. D
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Page 4 of 60
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August 2006
ADI [ ADI ]
