ADSP-BF531/ADSP-BF532
TABLE OF CONTENTS
General Description ................................................. 4
Portable Low Power Architecture ............................. 4
System Integration ................................................ 4
ADSP-BF531/ADSP-BF532 Processor Peripherals ........ 4
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 9
Watchdog Timer .................................................. 9
Timers ............................................................. 10
Serial Ports (SPORTs) .......................................... 10
Serial Peripheral Interface (SPI) Port ....................... 10
UART Port ........................................................ 10
Programmable Flags (PFx) .................................... 11
Parallel Peripheral Interface ................................... 11
Dynamic Power Management ................................ 12
Voltage Regulation .............................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 14
Development Tools ............................................. 15
Designing an Emulator-Compatible Processor Board .. 16
Related Documents ............................................. 16
Pin Descriptions .................................................... 17
Specifications ........................................................ 20
Operating Conditions .......................................... 20
Electrical Characteristics ....................................... 21
Absolute Maximum Ratings .................................. 22
Package Information ........................................... 22
ESD Sensitivity ................................................... 22
Timing Specifications .......................................... 23
Clock and Reset Timing .................................... 24
Asynchronous Memory Read Cycle Timing ........... 25
Asynchronous Memory Write Cycle Timing .......... 26
SDRAM Interface Timing .................................. 27
External Port Bus Request and Grant Cycle Timing .. 28
Parallel Peripheral Interface Timing ..................... 29
Serial Ports ..................................................... 32
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing ...... 39
Programmable Flags Cycle Timing ....................... 40
Timer Cycle Timing .......................................... 41
JTAG Test and Emulation Port Timing .................. 42
Output Drive Currents ......................................... 43
Power Dissipation ............................................... 45
Test Conditions .................................................. 45
Environmental Conditions .................................... 48
160-Ball BGA Pinout ............................................... 50
169-Ball PBGA Pinout ............................................. 53
176-Lead LQFP Pinout ............................................ 56
Outline Dimensions ................................................ 58
Ordering Guide ..................................................... 60
Serial Peripheral Interface (SPI) Port
—Master Timing .......................................... 37
Serial Peripheral Interface (SPI) Port
—Slave Timing ............................................. 38
Rev. D
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Page 2 of 60
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August 2006
ADI [ ADI ]
