ADSP-BF531/ADSP-BF532
Parallel Peripheral Interface Timing
Table 20 and Figure 15 on Page 29 describe parallel peripheral
interface operations.
Table 20. Parallel Peripheral Interface Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min Max Min
Max
Unit
Timing Requirements
tPCLKW
tPCLK
PPI_CLK Width
PPI_CLK Period1
6.0
6.0
ns
ns
ns
15.0
6.0
15.0
4.0
tSFSPE
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
tHFSPE
tSDRPE
tHDRPE
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
1.0
3.5
1.5
1.0
3.5
1.5
ns
ns
ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
8.0
9.0
8.0
9.0
ns
ns
ns
ns
1.7
1.8
1.7
1.8
1 PPI_CLK frequency cannot exceed fSCLK/2
FRAME
SYNC IS
DRIVEN
OUT
DATA0
IS
SAMPLED
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
t
DFSPE
t
HOFSPE
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
t
t
SDRPE
HDRPE
PPI_DATA
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing
Rev. D
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Page 29 of 60
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August 2006
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