ADSP-BF531/ADSP-BF532
SDRAM Interface Timing
Table 18. SDRAM Interface Timing
1
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min
Max
Unit
2.1
0.0
10.0
2.5
2.5
6.0
1.0
6.0
1.0
1.0
1.0
4.0
1.5
0.8
7.5
2.5
2.5
4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
SSDAT
DATA Setup Before CLKOUT
t
HSDAT
DATA Hold After CLKOUT
Switching Characteristics
t
SCLK
CLKOUT Period
2
t
SCLKH
CLKOUT Width High
CLKOUT Width Low
t
SCLKL
t
DCAD
Command, ADDR, Data Delay After CLKOUT
3
t
HCAD
Command, ADDR, Data Hold After CLKOUT
1
t
DSDAT
Data Disable After CLKOUT
t
ENSDAT
Data Enable After CLKOUT
1
2
SDRAM timing for
T
JUNCTION
=
125°C is limited to 100 MHz.
Refer to
for maximum f
SCLK
at various V
DDINT
.
3
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
t
SCLK
CLKOUT
t
SCLKH
t
SSDAT
t
H SDAT
DATA(IN)
t
SCLKL
t
DC AD
t
ENSDAT
DATA(OUT)
t
DSDAT
t
HCAD
t
DCAD
CMND ADDR
(OUT)
t
HCAD
NOTE: COMMAND =
SRAS, SCAS, SWE,
SDQM,
SMS,
SA10, SCKE.
Figure 13. SDRAM Interface Timing
Rev. D |
Page 27 of 60 |
August 2006
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