ADSP-BF531/ADSP-BF532
Programmable Flags Cycle Timing
and
describe programmable flag operations.
Table 27. Programmable Flags Cycle Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min
Max Min
Max
Unit
t
SCLK
+ 1
6
t
SCLK
+ 1
6
ns
ns
Parameter
Timing Requirement
t
WFI
Flag Input Pulse Width
Switching Characteristic
t
DFO
Flag Output Delay from CLKOUT Low
CLKOUT
t
DFO
PF (OUTPUT)
FLAG OUTPUT
t
WFI
PF (INPUT)
FLAG INPUT
Figure 25. Programmable Flags Cycle Timing
Rev. D |
Page 40 of 60 |
August 2006