ADSP-BF531/ADSP-BF532
Although the ADSP-BF531/ADSP-BF532 processor provides a
default mapping, the user can alter the mappings and priorities
of interrupt events by writing the appropriate values into the
interrupt assignment registers (IAR). Table 3 describes the
inputs into the SIC and the default mappings into the CEC.
preventing the processor from servicing the event even
though the event may be latched in the ILAT register. This
register may be read or written while in supervisor mode.
(Note that general-purpose interrupts can be globally
enabled and disabled with the STI and CLI instructions,
respectively.)
Table 3. System Interrupt Controller (SIC)
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
Peripheral Interrupt Event
PLL Wakeup
Default Mapping
IVG7
DMA Error
IVG7
PPI Error
IVG7
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3.
SPORT 0 Error
IVG7
SPORT 1 Error
IVG7
SPI Error
IVG7
• SIC interrupt mask register (SIC_IMASK) – This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servic-
ing the event.
UART Error
IVG7
Real-Time Clock
IVG8
DMA Channel 0 (PPI)
DMA Channel 1 (SPORT 0 Receive)
DMA Channel 2 (SPORT 0 Transmit)
DMA Channel 3 (SPORT 1 Receive)
DMA Channel 4 (SPORT 1 Transmit)
DMA Channel 5 (SPI)
DMA Channel 6 (UART Receive)
DMA Channel 7 (UART Transmit)
Timer 0
IVG8
IVG9
IVG9
IVG9
IVG9
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
Timer 1
• SIC interrupt wakeup enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
mation, see Dynamic Power Management on Page 12.)
Timer 2
PF Interrupt A
PF Interrupt B
DMA Channels 8 and 9
(Memory DMA Stream 1)
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
DMA Channels 10 and 11
(Memory DMA Stream 0)
IVG13
IVG13
Software Watchdog Timer
Event Control
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
The ADSP-BF531/ADSP-BF532 processor provides the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 16 bits wide:
• CEC interrupt latch register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
DMA CONTROLLERS
The ADSP-BF531/ADSP-BF532 processor has multiple, inde-
pendent DMA controllers that support automated data transfers
with minimal overhead for the processor core. DMA transfers
can occur between the ADSP-BF531/ADSP-BF532 processor’s
internal memories and any of its DMA-capable peripherals.
• CEC interrupt mask register (IMASK) – The IMASK regis-
ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event,
Rev. D
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Page 8 of 60
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August 2006
ADI [ ADI ]
