ADSP-2181
• SPORT s support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCIT T recommendation G.711.
#
of
P ins
P in
Nam e(s)
Input/
O utput Function
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
CLKOUT
SPORT 0
SPORT 1
1
5
5
O
Processor Clock Output
I/O
I/O
Serial Port I/O Pins
• SPORT s can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
Serial Port 1 or T wo External
IRQs, Flag In and Flag Out
IRD, IWR
IS
2
1
1
I
I
I
IDMA Port Read/Write Inputs
IDMA Port Select
• SPORT 0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
IAL
IDMA Port Address Latch
Enable
• SPORT 1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. T he
internally generated serial clock may still be used in this
configuration.
IAD
16
1
I/O
O
IDMA Port Address/Data Bus
IACK
IDMA Port Access Ready
Acknowledge
PWD
1
1
I
Power-Down Control
Power-Down Control
P in D escr iptions
T he ADSP-2181 is available in 128-lead T QFP and 128-lead
PQFP packages.
PWDACK
O
FL0, FL1,
FL2
3
8
1
1
1
1
1
1
1
1
1
11
6
O
I/O
*
Output Flags
P IN FUNCTIO N D ESCRIP TIO NS
#
PF7:0
EE
Programmable I/O Pins
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
Ground Pins
P in
of
Input/
O utput Function
EBR
*
Nam e(s)
P ins
EBG
*
Address
14
O
Address Output Pins for Program,
Data, Byte, and I/ O Spaces
Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)
ERESET
EMS
*
*
Data
24
I/O
EINT
ECLK
ELIN
ELOUT
GND
VDD
*
*
*
RESET
IRQ2
1
1
I
I
Processor Reset Input
*
Edge- or Level-Sensitive
Interrupt Request
–
–
Power Supply Pins
IRQL0,
IRQL1
*T hese ADSP-2181 pins must be connected only to the EZ-ICE connector in
the target system. T hese pins have no function except during emulation, and
do not require pull-up or pull-down resistors.
2
1
I
I
Level-Sensitive Interrupt
Requests
IRQE
Edge-Sensitive Interrupt
Request
Inter r upts
T he interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
T he ADSP-2181 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT 1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT , for a total of six external interrupts. T he ADSP-
2181 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. T he interrupt levels are internally prioritized and
individually maskable (except power down and reset). T he
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge sensitive. T he priorities and vector
addresses of all interrupts are shown in T able I.
BR
1
1
1
1
1
1
1
1
1
1
1
1
I
Bus Request Input
BG
O
O
O
O
O
O
O
O
O
I
Bus Grant Output
BGH
PMS
DMS
BMS
IOMS
CMS
RD
Bus Grant Hung Output
Program Memory Select Output
Data Memory Select Output
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Memory Map Select Input
Boot Option Control Input
WR
MMAP
BMODE
I
CLKIN,
XT AL
2
I
Clock or Quartz Crystal Input
REV. D
–4–
ADI [ ADI ]
