ADSP-2181
ADSP-2181 can fetch an operand from program memory and
the next instruction in the same cycle.
T he ADSP-2181 provides up to 13 general-purpose flag pins.
T he data input and output pins on SPORT 1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
In addition to the address and data bus for external memory
connection, the ADSP-2181 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. T he IDMA
port is made up of 16 data/address pins and five control pins.
T he IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
A programmable interval timer generates periodic interrupts. A
16-bit count register (T COUNT ) is decremented every n pro-
cessor cycles, where n is a scaling value stored in an 8-bit regis-
ter (T SCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (T PERIOD).
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). T he BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
Ser ial P or ts
T he ADSP-2181 incorporates two complete synchronous serial
ports (SPORT 0 and SPORT 1) for serial communications and
multiprocessor communication.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH and BG).
One execution mode (Go Mode) allows the ADSP-2181 to con-
tinue running from on-chip memory. Normal execution mode
requires the processor to halt while buses are granted.
Here is a brief list of the capabilities of the ADSP-2181 SPORTs.
Refer to the ADSP-2100 Family User’s Manual, Third Edition for
further details.
• SPORT s are bidirectional and have a separate, double-
buffered transmit and receive section.
T he ADSP-2181 can respond to 13 possible interrupts, eleven
of which are accessible at any given time. T here can be up to six
external interrupts (one edge-sensitive, two level-sensitive and
three configurable) and seven internal interrupts generated by
the timer, the serial ports (SPORT s), the Byte DMA port and
the power-down circuitry. T here is also a master RESET signal.
• SPORT s can use an external serial clock or generate their
own serial clock internally.
• SPORT s have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
21xx CORE
ADSP-2181 INTEGRATION
POWER-
DOWN
2
CONTROL
LOGIC
INSTRUCTION
REGISTER
PROGRAM
SRAM
DATA
SRAM
8
BYTE
DMA
CONTROLLER
PROGRAMMABLE
I/O
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
3
PROGRAM
SEQUENCER
FLAGS
PMA BUS
DMA BUS
14
14
PMA BUS
14
MUX
DMA BUS
EXTERNAL
ADDRESS
BUS
PMD BUS
DMD BUS
24
PMD BUS
EXTERNAL
DATA
BUS
BUS
EXCHANGE
MUX
DMD
BUS
24
16
INPUT REGS
INPUT REGS
INPUT REGS
INPUT REGS
INPUT REGS
SHIFTER
COMPANDING
CIRCUITRY
16
INTERNAL
DMA
PORT
ALU
ALU
MAC
MAC
TIMER
TRANSMIT REG
TRANSMIT REG
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
RECEIVE REG
RECEIVE REG
4
SERIAL
PORT 0
SERIAL
PORT 0
16
INTERRUPTS
R BUS
5
5
Figure 1. ADSP-2181 Block Diagram
–3–
REV. D
ADI [ ADI ]
