ADSP-21065L
POWER DISSIPATION ADSP-21065L
These specifications apply to the internal power portion of V
DD
only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note SHARC Power Dissipation Measurements.
Specifications are based on the following operating scenarios:
Table II. Internal Current Measurements
Operation
Instruction Type
Instruction Fetch
Core Memory Access
Internal Memory DMA
Peak Activity
(I
DDINPEAK
)
Multifunction
Cache
2 per Cycle (DM and PM)
1 per Cycle
High Activity
(I
DDINHIGH
)
Multifunction
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
Low Activity (I
DDINLOW
)
Single Function
Internal Memory
None
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK
¥
I
DDINPEAK
+ %HIGH
¥
I
DDINHIGH
+ %LOW
¥
I
DDINLOW
+ %IDLE
¥
I
DDIDLE
=
POWER CONSUMPTION
(See note 4 below Table III.)
OR %PEAK
¥
I
DDINPEAK
+ %HIGH
¥
I
DDINHIGH
+ %LOW
¥
I
DDINLOW
+ %IDLE16
¥
I
DDIDLE16
=
POWER CONSUMPTION
(See note 5 below Table III.)
Table III. Internal Current Measurement Scenarios
Parameter
I
DDINPEAK
I
DDINHIGH
I
DDINLOW
I
DDIDLE
I
DDIDLE16
Supply Current (Internal)
1
Supply Current (Internal)
2
Supply Current (Internal)
3
Supply Current (IDLE)
4
Supply Current (IDLE16)
5
Test Conditions
t
CK
= 33 ns, V
DD
= max
t
CK
= 30 ns, V
DD
= max
t
CK
= 33 ns, V
DD
= max
t
CK
= 30 ns, V
DD
= max
t
CK
= 33 ns, V
DD
= max
t
CK
= 30 ns, V
DD
= max
t
CK
= 33 ns, V
DD
= max
t
CK
= 30 ns, V
DD
= max
V
DD
= max
Max
470
510
275
300
240
260
150
155
50
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
1
The test program used to measure I
DDINPEAK
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
I
DDINHIGH
is a composite average based on a range of high activity code.
3
I
DDINLOW
is a composite average based on a range of low activity code.
4
IDLE denotes ADSP-21065L state during execution of IDLE instruction.
5
IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction.
TIMING SPECIFICATIONS
General Notes
Two speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a
CLKIN frequency of 30 MHz (t
CK
= 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min–
max range of the t
CK
specification; see Clock Input below). DT is the difference between the actual CLKIN period and a CLKIN
period of 33.3 ns:
DT
= (t
CK
– 33.3)/32
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addi-
tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical varia-
tions and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.
See Figure 27 in Equivalent Device Loading for AC Measurements (Includes All Fixtures) for voltage reference levels.
REV. C
–13–
AD [ ANALOG DEVICES ]
