ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
CIRCUIT INFORMATION
MANUAL RESET
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
INPUT (WDI)
WATCHDOG
TIMER
MR
The
switch, to generate a processor reset. The input is effectively
MR
input allows other reset sources, such as a manual reset
WATCHDOG
OUTPUT (WDO)
debounced by the timeout period (200 ms typical). The
input is TTL-/CMOS-compatible; it can also be driven by any
V
RESET AND
WATCHDOG
TIMEBASE
CC
70μA
MR
logic reset output. If unused, the
left floating.
input can be tied high or
MR
RESET,
(P = RESET)
RESET
GENERATOR
V
CC
V
V
RT
V
RT
CC
V
*
REF
ADM706P/ADM706R/
ADM706S/ADM706T
POWER-FAIL
INPUT (PFI)
tRS
tRS
POWER-FAIL
OUTPUT (PFO)
1.25V
RESET
MR
*
VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
Figure 13. ADM706 Functional Block Diagram
MR EXTERNALLY
DRIVEN LOW
V
CC
WDO
70μA
RESET
RESET
NOTES
RESET = COMPLEMENT OF RESET
MR
RESET
GENERATOR
V
CC
RESET MR
WDO
Timing
Figure 15.
,
, and
V
*
REF
ADM708R/ADM708S/
ADM708T
POWER-FAIL
INPUT (PFI)
WATCHDOG TIMER (ADM706x)
POWER-FAIL
OUTPUT (PFO)
1.25V
The watchdog timer circuit is used to monitor the activity of the
microprocessor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the timeout
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Figure 14. ADM708 Functional Block Diagram
POWER-FAIL RESET
WDO
period (1.6 seconds), the watchdog output ( ) is driven low.
RESET
The reset output provides a reset (RESET or
) output
WDO
output is connected to a nonmaskable interrupt (NMI)
The
signal to the microprocessor whenever the VCC input is below
the reset threshold. The actual reset threshold voltage is dependent
on whether a P, R, S, or T suffix device is used. An internal timer
holds the reset output active for 200 ms after the voltage on VCC
rises above the threshold. This is intended as a power-on reset
signal for the microprocessor. It allows time for both the power
supply and the microprocessor to stabilize after power-up. If a
power supply brownout or interruption occurs, the reset line is
similarly activated and remains active for 200 ms after the supply
recovers. If another interruption occurs during an active reset
period, the reset timeout period continues for an additional 200 ms.
on the processor. Therefore, if the watchdog timer times out, an
interrupt is generated. The interrupt service routine is used to
rectify the problem.
The watchdog timer is cleared either by a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
RESET
detected. The timer is also cleared by RESET/
going
active. Therefore, the watchdog timeout period begins after
reset goes inactive.
WDO
When VCC falls below the reset threshold,
is forced low
whether or not the watchdog timer has timed out. Normally,
RESET
this generates an interrupt, but it is overridden by RESET/
going active.
The reset output is guaranteed to remain valid with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
tWP
tWD
tWD
tWD
WDI
The ADM706P provides an active high RESET signal; the
RESET
ADM706R/ADM706S/ADM706T provide an active low
signal; and the ADM708R/ADM706S/ADM706T provide both
RESET
WDO
RESET and
.
RESET EXTERNALLY
TRIGGERED BY MR
RESET
tRS
Figure 16. Watchdog Timing
Rev. D | Page 10 of 16
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