ADM690–ADM695
Table I. AD M691, AD M693, AD M695 Reset P ulse Width and Watchdog Tim eout Selections
Watchdog Tim eout P eriod
Im m ediately
Reset Active P eriod
O SC SEL
O SC IN
Norm al
After Reset
AD M691/AD M693
AD M695
Low
Low
External Clock Input
External Capacitor
1024 CLKS
260 ms × C/47 pF 1.04 s × C/47 pF
100 ms
1.6 s
4096 CLKS
512 CLKS
130 ms × C/47 pF
50 ms
2048 CLKS
520 ms × C/47 pF
200 ms
Floating or High Low
Floating or High Floating or High
1.6 s
1.6 s
50 ms
200 ms
NOT E
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. T he nominal
internal oscillator frequency is 10.24 kHz. T he nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
T he watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
8
OSC SEL
On the ADM694 the watchdog timeout period is also 1.6 sec-
ADM691
onds but the reset pulse width is fixed at 200 ms. The ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in T able I. Figure 4 shows the various oscillator configurations
which can be used to adjust the reset pulse width and watchdog
timeout period.
ADM693
ADM695
7
OSC IN
COSC
T he internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset, the timeout period is 1.6
seconds. T his gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. T he software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
Figure 4b. External Capacitor
8
NC
NC
OSC SEL
ADM691
ADM693
ADM695
7
OSC IN
Watchdog O utput (WD O )
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
T he Watchdog Output WDO (ADM691/ADM693/ADM695)
provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
on the Watchdog Input. WDO is also set high when VCC goes
below the reset threshold.
8
NC
OSC SEL
ADM691
ADM693
ADM695
8
OSC SEL
ADM691
ADM693
ADM695
7
OSC IN
CLOCK
0 TO 250kHz
7
OSC IN
Figure 4d. Internal Oscillator (100 m s Watchdog)
Figure 4a. External Clock Source
REV. A
–7–
ADI [ ADI ]
