ADM3485E
V
CC
R
L
= 110Ω
S1
0V OR 3V
D
C
L
= 50pF
2
GENERATOR
1
OUT
GENERATOR
1
50Ω
V
ID
R
OUT
C
L
= 15pF
2
50Ω
1.5V
0V
V
OM
=
V
CC
2
1
PPR = 250kHz, 50% DUTY CYCLE,
t
≤ 6.0ns, Z = 50Ω.
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
1
PPR = 250kHz, 50% DUTY CYCLE,
t
≤ 6.0ns, Z = 50Ω.
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
3V
IN
1.5V
1.5V
0V
IN
1.5V
1.5V
3V
0V
t
PSL
OUT
V
OM
t
PLZ
V
CC
0.25V
03338-043
t
RPLH
t
RPHL
V
CC
03338-044
V
OL
OUT
V
OM
V
OM
0V
Figure 9. Driver Enable and Disable Times (t
PZL
, t
PSL
, t
PLZ
)
+1.5V
–1.5V
S3
V
ID
1kΩ
R
C
L2
S2
S1
Figure 10. Receiver Propagation Delays
V
CC
GENERATOR
1
50Ω
1
PPR = 250kHz, 50% DUTY CYCLE,
t
≤ 6.0ns, Z = 50Ω.
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
+3V
IN
+1.5V
t
RPZH
t
RPSH
OUT
+1.5V
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
+3V
IN
+1.5V
t
RPZL
t
RPSL
OUT
+1.5V
0V
S1 CLOSED
S2 OPEN
S3 = –1.5V
V
OH
V
CC
0V
V
OL
+3V
IN
+1.5V
+3V
S1 OPEN
S2 CLOSED
S3 = +1.5V
IN
+1.5V
0V
0V
S1 CLOSED
S2 OPEN
S3 = –1.5V
t
RPHZ
OUT
+0.25V
t
RPLZ
V
OH
OUT
03338-045
V
CC
0V
+0.25V
V
OL
Figure 11. Receiver Enable and Disable Times
Rev. D | Page 8 of 16
AD [ ANALOG DEVICES ]
