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ADM3486EARZ-REEL7 参数 Datasheet PDF下载

ADM3486EARZ-REEL7图片预览
型号: ADM3486EARZ-REEL7
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V , 【 15千伏ESD保护,半双工和全双工, RS - 485 / RS -422收发器 [3.3 V, 【15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers]
分类和应用:
文件页数/大小: 20 页 / 536 K
品牌: ADI [ ADI ]
 浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第4页浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第5页浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第6页浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第7页浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第9页浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第10页浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第11页浏览型号ADM3486EARZ-REEL7的Datasheet PDF文件第12页  
ASM3483ꢁ/ASM3486ꢁ/ASM3488ꢁ/ASM3490ꢁ/ASM349±ꢁ  
-IN CONFIGURATIONE ANS FUNCTION SꢁECRI-TIONE  
NC  
RO  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
V
V
CC  
CC  
RE  
A
ADM3491E  
TOP VIEW  
(Not to Scale)  
DE  
B
RO  
RE  
DE  
DI  
1
2
3
4
8
7
6
5
V
V
1
2
3
4
8
7
6
5
A
B
Z
DI  
Z
CC  
CC  
ADM3483E/  
ADM3486E  
ADM3488E/  
ADM3490E  
B
RO  
DI  
GND  
GND  
Y
A
TOP VIEW  
(Not to Scale)  
8
NC  
TOP VIEW  
(Not to Scale)  
GND  
GND  
Y
NC = NO CONNECT  
Figure 4. ADM3483E/ADM3486E  
Pin Configuration  
Figure 5. ADM3488E/ADM3490E  
Pin Configuration  
Figure 6. ADM3491E  
Pin Configuration  
Table 8. Pin Function Descriptions  
ADM3483E/  
ADM3486E  
Pin No.  
ADM3488E/  
ADM3490E  
Pin No.  
ADM3491E  
Pin No.  
Mnemonic Description  
Receiver Output. If A > B by 200 mV, RO is high; if A < B by 200 mV,  
RO is low.  
1
2
2
RO  
2
N/A  
3
RE  
Receiver Output Enable. A low level enables the receiver output. A high  
level places it in a high impedance state. If RE is high and DE is low, the  
device enters a low power shutdown mode.  
3
4
N/A  
3
4
5
DE  
DI  
Driver Output Enable. A high level enables the driver differential A and B  
outputs. A low level places it in a high impedance state. If RE is high and DE  
is low, the device enters a low power shutdown mode.  
Driver Input. With a half-duplex part when the driver is enabled, a logic low  
on DI forces A low and B high; a logic high on DI forces A high and B low.  
With a full-duplex part when the driver is enabled, a logic low on DI forces Y  
low and Z high; a logic high on DI forces Y high and Z low.  
5
N/A  
6
N/A  
N/A  
7
N/A  
8
4
5
N/A  
8
6
N/A  
7
1
6, 7  
9
N/A  
12  
10  
N/A  
11  
GND  
Y
A
A
Z
B
B
VCC  
NC  
Ground.  
Noninverting Driver Output.  
Noninverting Receiver Input A and Noninverting Driver Output A.  
Noninverting Receiver Input A.  
Inverting Driver Output.  
Inverting Receiver Input B and Inverting Driver Output B.  
Inverting Receiver Input B.  
Power Supply, 3.3 V 0.3 V. Bypass VCC to GND with a 0.1 μF capacitor.  
No Connect. Not internally connected. Can be connected to GND.  
13, 14  
1, 8  
N/A  
N/A  
Rev. A | Page 8 of 20  
 
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