ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
1
RO
2
RE
3
DE
4
14
V
CC
13
V
CC
12
A
ADM3491E
RO
1
RE
2
DE
3
DI
4
ADM3483E/
ADM3486E
TOP VIEW
(Not to Scale)
8
7
6
5
V
CC
B
06284-004
V
CC 1
RO
2
DI
3
GND
4
ADM3488E/
ADM3490E
TOP VIEW
(Not to Scale)
8
7
6
5
A
B
06284-005
11
B
TOP VIEW
(Not to Scale)
10
Z
DI
5
9
8
GND
6
GND
7
Y
NC
06284-006
A
GND
Z
Y
NC = NO CONNECT
Figure 4. ADM3483E/ADM3486E
Pin Configuration
Figure 5. ADM3488E/ADM3490E
Pin Configuration
Figure 6. ADM3491E
Pin Configuration
Table 8. Pin Function Descriptions
ADM3483E/
ADM3486E
Pin No.
1
2
ADM3488E/
ADM3490E
Pin No.
2
N/A
ADM3491E
Pin No.
2
3
Mnemonic
RO
RE
3
N/A
4
DE
4
3
5
DI
5
N/A
6
N/A
N/A
7
N/A
8
N/A
4
5
N/A
8
6
N/A
7
1
N/A
6, 7
9
N/A
12
10
N/A
11
13, 14
1, 8
GND
Y
A
A
Z
B
B
V
CC
NC
Description
Receiver Output. If A > B by 200 mV, RO is high; if A < B by 200 mV,
RO is low.
Receiver Output Enable. A low level enables the receiver output. A high
level places it in a high impedance state. If RE is high and DE is low, the
device enters a low power shutdown mode.
Driver Output Enable. A high level enables the driver differential A and B
outputs. A low level places it in a high impedance state. If RE is high and DE
is low, the device enters a low power shutdown mode.
Driver Input. With a half-duplex part when the driver is enabled, a logic low
on DI forces A low and B high; a logic high on DI forces A high and B low.
With a full-duplex part when the driver is enabled, a logic low on DI forces Y
low and Z high; a logic high on DI forces Y high and Z low.
Ground.
Noninverting Driver Output.
Noninverting Receiver Input A and Noninverting Driver Output A.
Noninverting Receiver Input A.
Inverting Driver Output.
Inverting Receiver Input B and Inverting Driver Output B.
Inverting Receiver Input B.
Power Supply, 3.3 V ± 0.3 V. Bypass V
CC
to GND with a 0.1 μF capacitor.
No Connect. Not internally connected. Can be connected to GND.
Rev. A | Page 8 of 20
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