ADM2209E
(Electrical Fast Transient) discharges. A simplified schematic of
the protection structure is shown in Figures 22a and 22b. Each
input and output contains two back-to-back high speed clamping
diodes. During normal operation with maximum RS-232 signal
levels, the diodes have no effect as one or the other is reverse-
biased, depending on the polarity of the signal. If, however, the
voltage exceeds about ±50 V, reverse breakdown occurs and the
voltage is clamped at this level. The diodes are large p-n junctions
designed to handle the instantaneous current surge which can
exceed several amperes.
product connected to the I-O port. Traditional ESD test meth-
ods such as the MIL-STD-883B method 3015.7 do not fully
test a product’s susceptibility to this type of discharge. This test
was intended to test a product’s susceptibility to ESD damage
during handling. Each pin is tested with respect to all other
pins. There are some important differences between the tradi-
tional test and the IEC test:
(a) The IEC test is much more stringent in terms of discharge
energy. The peak current injected is over four times greater.
(b) The current rise time is significantly faster in the IEC test.
(c) The IEC test is carried out while power is applied to the device.
The transmitter outputs and receiver inputs have a similar pro-
tection structure. The receiver inputs can also dissipate some of
the energy through the internal 5 kΩ resistor to GND as well as
through the protection diodes.
It is possible that the ESD discharge could induce latch-up in the
device under test. This test is therefore more representative of a
real-world I-O discharge where the equipment is operating nor-
mally with power applied. For maximum peace of mind, however,
both tests should be performed, to ensure maximum protection
both during handling and later, during field service.
The protection structure achieves ESD protection up to ±15 kV
and EFT protection up to ±2 kV on all RS-232 I-O lines. The
methods used to test the protection scheme are discussed later.
R1
R2
HIGH
VOLTAGE
GENERATOR
RECEIVER
Rx
INPUT
D1
DEVICE
UNDER TEST
R
IN
C1
D2
ESD TEST METHOD
R2
C1
H. BODY MIL-STD-883B
IEC1000-4-2
1.5k⍀
330⍀
100pF
150pF
Figure 22a. Receiver Input Protection Scheme
Figure 23. ESD Test Standards
TRANSMITTER
Tx
OUTPUT
D1
100
90
D2
Figure 22b. Transmitter Output Protection Scheme
ESD TESTING (IEC1000-4-2)
IEC1000-4-2 (previously 801-2) specifies compliance testing
using two coupling methods, contact discharge and air-gap
discharge. Contact discharge calls for a direct connection to the
unit being tested. Air-gap discharge uses a higher test voltage
but does not make direct contact with the unit under test. With
air discharge, the discharge gun is moved towards the unit un-
der test developing an arc across the air gap, hence the term air-
discharge. This method is influenced by humidity, temperature,
barometric pressure, distance and rate of closure of the discharge
gun. The contact-discharge method, while less realistic, is more
repeatable and is gaining acceptance in preference to the air-gap
method.
36.8
10
tDL
tRL
TIME t
Figure 24. Human Body Model ESD Current Waveform
100
90
Although very little energy is contained within an ESD pulse,
the extremely fast rise time coupled with high voltages can cause
failures in unprotected semiconductors. Catastrophic destruc-
tion can occur immediately as a result of arcing or heating. Even
if catastrophic failure does not occur immediately, the device
may suffer from parametric degradation, which may result in
degraded performance. The cumulative effects of continuous
exposure can eventually lead to complete failure.
10
0.1 TO 1ns
TIME t
30ns
I-O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I-O cable can result in a static dis-
charge that can damage or completely destroy the interface
60ns
Figure 25. IEC1000-4-2 ESD Current Waveform
REV. 0
–9–
ADI [ ADI ]
