ADM1026
3.3VSTBY
Note that the
pin is bidirectional, so
may be
THERM
THERM
pulled low externally as an input. This causes the PWM and
DAC outputs to go to full scale until is returned high
~1V
~1V
THERM
as an input, set Bit 0 of Configuration
3.3VMAIN
again. To disable
THERM
Register 3 (Reg. 07h). This configures Pin 42 as GPIO16 and
prevents a low on Pin 42 from driving the fans at full speed.
RESETSTBY
TEMPERATURE
RESETMAIN
180ms
180ms
THERM LIMIT
POWER-ON RESET
THERM LIMIT – 5°C
Figure 55. Operation of Offset Outputs
THERM
INT
NAND TREE TESTS
A NAND tree is provided in the ADM1026 for automated test
equipment (ATE) board-level connectivity testing. This allows
the functionality of all digital inputs to be tested in a simple
manner and any pins that are nonfunctional or shorted together
to be identified. The structure of the NAND tree is shown in
Figure 56. The device is placed into NAND tree test mode by
powering up with Pin 25 held high. This pin is sampled
automatically after power-up, and if it is connected high, then
the NAND test mode is invoked.
INT CLEARED BY STATUS REG 1 READ,
BIT 2 OF CONFIG. REG. 1 SET, OR ARA
INT
THERM
Event
Figure 54. Assertion of
Due to
Reset Input and Outputs
The ADM1026 has two active low, power-on reset outputs,
RESETMAIN
and
. These operate as follows.
RESETSTBY
GPIO8
monitors 3.3 V STBY. At power-up,
is
RESETSTBY
RESETSTBY
GPIO9
FAN0
asserted (pulled low) until 180 ms after 3.3 V STBY rises above
the reset threshold.
GPIO10
FAN1
GPIO11
FAN2
monitors 3.3 V MAIN. This means that at power-
RESETMAIN
up,
is asserted (pulled low) until 180 ms after
RESETMAIN
GPIO12
GPIO13
GPIO14
GPIO15
INT
CI
FAN3
FAN4
FAN5
FAN6
3.3 V MAIN rises above the reset threshold.
If 3.3 V MAIN rises with or before DVCC,
RESETMAIN
is negated.
remains asserted until 180 ms after
RESETSTBY
SDA
SCL
can also function as a RESET input. Pulling this
RESETMAIN
pin low resets the registers, which are initialized to their default
values by a software reset. (See the Software Reset Function
section for register details).
FAN7
NTESTOUT
GPIO16
Figure 56. NAND Tree
Note that the 3.3 V STBY pin supplies power to the ADM1026.
In applications that do not require monitoring of a 3.3 V STBY
and 3.3 V MAIN supply, these two pins should be connected
together (3.3 V MAIN should not be left floating).
The NAND tree test may be carried out in one of two ways.
1. Start with all inputs low and take them high in turn,
starting with the input nearest to NTEST_OUT
(GPIO16/
) and working back up the tree to the
THERM
To ensure that the 3.3 V STBY pin does not become backdriven,
the 3.3 V STBY supply should power on before all other voltages
in the system.
input furthest from NTESTOUT (
). This should give
INT
the characteristic output pattern shown in Figure 57, with
NTESTOUT toggling each time an input is taken high.
See Table 3 for more information about pin configuration.
2. Start with all inputs high and take them low in turn,
starting with the input furthest from NTEST_OUT (
)
INT
and working down the tree to the input nearest to
NTEST_OUT (GPIO16/
). This should give a
THERM
similar output pattern to Figure 58.
Rev. A | Page 3± of 56
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