ADM1026
Status Register 4 also stores inputs from two other interrupt
sources that operate in a different way from the other status bits.
If automatic fan speed control (AFC) is enabled, Bit 4 of Status
Register 4 is set whenever a fan starts or stops. This bit causes a
The GPIO and CI status bits, after mask gating, are OR’ed
together and OR’ed with other interrupt sources to produce the
output. GPIO and CI interrupts are not latched and cannot
be cleared by normal interrupt clearing. They can only be
cleared by masking the status bits or by removing the source of
the interrupt.
INT
one-off
output as shown in Figure 52. It is cleared during
INT
the next monitoring cycle and if
has been cleared, it does
INT
not cause
to be reasserted.
INT
ENABLING AND CLEARING INTERRUPTS
FAN ON
FAN OFF
INT
The
output is enabled when Bit 1 of Configuration
INT
Register 1 (INT_Enable) is high, and Bit 2 (INT_Clear) is low.
INT
may be cleared if
•
Status Register 1 is read. Ideally, if polling the status
registers trying to identify interrupt sources, Status
Register 1 should be polled last, because a read of Status
Register 1 clears all the other interrupt status registers.
The ADM1026 receives the alert response address (ARA)
(0001 100) over the SMBus.
INT CLEARED BY STATUS REGULAR 1 READ, BIT 2
OF CONFIGURATION REGULAR 1 SET, OR ARA
INT
Figure 52. Assertion of
Due to AFC Event
•
•
In a similar way, a change of state at the
output
THERM
(described in more detail later), sets Bit 3 of Status
Register 4 and causes a one-off output. A change of state at
Bit 2 of Configuration Register 1 is set.
INT
output also causes Bit 0 of Status Register 1, Bit 1
the
THERM
of Status Register 1, or Bit 0 of Status Register 4 to be set,
depending on which temperature channel caused the
Bidirectional
Pin
THERM
The ADM1026 has a second interrupt pin (GPIO16/
THERM
Pin 42) that responds only to critical thermal events. The
pin goes low whenever a limit is exceeded.
THERM
event. This bit is reset during the next monitoring cycle,
provided the temperature channel is within the normal high
and low limits.
THERM
This function is useful for CPU throttling or system shutdown.
In addition, whenever is activated, the PWM and DAC
THERM
THERM
outputs go full scale to provide fail-safe system cooling. This
output is enabled by setting Bit 4 of Configuration Register 1
Fan Inputs
Fan inputs generate interrupts in a similar way to analog/
temperature inputs, but as the analog/ temperature inputs and
fan inputs have different monitoring cycles, they have separate
interrupt circuits. As the speed of each fan is measured, the
output of the fan speed counter is stored in a value register. The
result is compared to the fan speed limit and is used to set or
clear a bit in Status Register 3. In this case, the fan is monitored
only for under-speed (fan counter > fan speed limit). Mask
Register 3 is used to mask fan interrupts. After mask gating, the
fan status bits are OR’ed together and used to set a latch, whose
(Register 00h). Whenever a
limit is exceeded, Bit 3 of
THERM
Status Register 4 (Reg 23h) is set, even if the
function
THERM
is disabled (Bit 4 of Configuration Register 1 = 0). In this case,
the status bit is set, but the PWM and DAC outputs are
THERM
not forced to full scale.
Three thermal limit registers are provided for the three
temperature sensors at Addresses 0Dh to 0Fh. These registers
are dedicated to the
function and none of the other
THERM
output is OR’ed with other interrupt sources to produce the
INT
limit registers have any effect on the
output.
THERM
output.
If any of the temperature measurements exceed the correspond-
Like the analog/temp interrupt, an
output caused by an
INT
out-of-limit fan speed measurement, once cleared, is not
reasserted until the end of the next monitoring cycle, although
other interrupt sources may cause to be asserted.
ing limit, is asserted (low) and the DAC and PWM
THERM
outputs go to maximum to drive any cooling fans to full speed.
To avoid cooling fans cycling on and off continually when the
temperature is close to the limit, a fixed hysteresis of 5°C is
INT
provided.
is only deasserted when the measured
GPIO and CI Pins. When GPIO pins are configured as inputs,
asserting a GPIO input (high or low, depending on polarity) sets
the corresponding GPIO status bit in Status Registers 5 and 6, or
Bit 7 of Status Register 4 (GPIO16). A chassis intrusion event
sets Bit 6 of Status Register 4.
THERM
temperature of all three sensors is 5°C below the limit.
Whenever the output changes, is asserted, as
shown in Figure 54. However, this is edge-triggered, so if
THERM
INT
INT
is subsequently cleared by one of the methods previously
described, it is not reasserted, even if
remains asserted.
THERM
to be reasserted only when it changes state.
INT
causes
THERM
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