ADG46+1/ADG46+3
TEST CIRCUITS
I
DS
V1
Sx
R
Dx
V
= V1/I
DS
S
ON
Figure 22. On Resistance
I
(OFF)
A
I
(OFF)
A
S
D
Sx
Dx
V
V
S
D
Figure 23. Off Leakage
I
(ON)
D
Sx
Dx
NC
A
V
D
NC = NO CONNECT
Figure 24. On Leakage
V
V
DD
DD
SS
0.1µF
0.1µF
V
V
SS
V
L
OUT
Sx
Dx
50%
50%
V
IN
ADG4612
R
300ꢀ
C
L
V
S
35pF
INx
90%
90%
V
OUT
GND
tOFF
tON
Figure 25. Switching Times
V
V
DD
DD
SS
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
V
SS
90%
90%
V
V
S1
D1
OUT1
OUT2
V
V
V
S1
OUT1
C
35pF
R
50ꢀ
L
L
S2
D2
V
S2
OUT2
C
35pF
R
50ꢀ
L
L
90%
90%
IN1,
IN2
0V
ADG4613
GND
tD
tD
Figure 26. Break-Before-Make Time Delay, tD
Rev. 0 | Page 14 of 24