ADG406/ADG407/ADG426
ADG426 TIMING DIAGRAMS
3V
WR
0V
50%
50%
3V
RS
0V
50%
50%
t
W
t
S
t
H
00026-009
t
W
t
OFF
(RS)
3V
A0, A1, A2, (A3)
EN
0V
2V
0.8V
SWITCH
OUTPUT
Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs
0V
Figure 5. Reset Pulse Width and Reset Turn Off Time
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
rs
, and the reset turn off
time, t
OFF
(RS).
Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V; t
R
= t
F
= 20 ns.
Rev. B | Page 7 of 20
00026-010
V
0
0.8V
0
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