欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADF4360-3BCPZRL 参数 Datasheet PDF下载

ADF4360-3BCPZRL图片预览
型号: ADF4360-3BCPZRL
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的合成器和VCO [Integrated Synthesizer and VCO]
分类和应用: 电信集成电路蜂窝电话电路电信电路信息通信管理
文件页数/大小: 24 页 / 317 K
品牌: ADI [ ADI ]
 浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第12页浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第13页浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第14页浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第15页浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第17页浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第18页浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第19页浏览型号ADF4360-3BCPZRL的Datasheet PDF文件第20页  
ADF4360-3  
Data Sheet  
and the bias currents of the VCO begins to settle. If these cur-  
rents have not settled to within 10% of their steady-state value,  
and if the N counter latch is then programmed, the VCO may  
not be able to oscillate at the desired frequency, which does not  
allow the band select logic to choose the correct frequency  
band, and the ADF4360-3 may not achieve lock. If the recom-  
mended interval is inserted, and the N counter latch is pro-  
grammed, the band select logic can choose the correct frequen-  
cy band, and the part locks to the correct frequency.  
POWER-UP  
Power-Up Sequence  
The correct programming sequence for the ADF4360-3 after  
power-up is:  
1. R counter latch  
2. Control latch  
3. N counter latch  
The duration of this interval is affected by the value of the ca-  
pacitor on the CN pin (Pin 14). This capacitor is used to reduce  
the close-in noise of the ADF4360-3 VCO. The recommended  
value of this capacitor is 10 μF. Using this value requires an in-  
terval of ≥ 5 ms between the latching in of the control latch bits  
and latching in of the N counter latch bits. If a shorter delay is  
required, this capacitor can be reduced. A slight phase noise  
penalty is incurred by this change, which is explained further  
in Table 10.  
Initial Power-Up  
Initial power-up refers to programming the part after the  
application of voltage to the AVDD, DVDD, VVCO, and CE pins. On  
initial power-up, an interval is required between programming  
the control latch and programming the N counter latch.  
This interval is necessary to allow the transient behavior of the  
ADF4360-3 during initial power-up to have settled. During  
initial power-up, a write to the control latch powers up the part,  
Table 10. CN Capacitance vs. Interval and Phase Noise  
CN Value  
Recommended Interval between Control Latch and N Counter latch  
Open-Loop Phase Noise @ 10 kHz Offset  
10 μF  
440 nF  
≥5 ms  
≥600 μs  
−87 dBc  
−86 dBc  
POWER-UP  
CLOCK  
R COUNTER  
LATCH DATA  
CONTROL  
LATCH DATA  
N COUNTER  
LATCH DATA  
DATA  
LE  
REQUIRED INTERVAL  
CONTROL LATCH WRITE TO  
N COUNTER LATCH WRITE  
Figure 16. ADF4360-3 Power-Up Timing  
Rev. C | Page 16 of 24  
 
 
 
 
 复制成功!