Data Sheet
ADF4360-3
Table 9. R Counter Latch
ANTI-
BACKLASH
PULSE
BAND
SELECT
CLOCK
CONTROL
BITS
14-BIT REFERENCE COUNTER
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10
R9
R8
R7
R6
R5
R4
R3
R2
R1 C2 (0) C1 (1)
R14
0
0
R13
R12
R3
0
0
0
1
.
.
.
1
1
1
1
R2
0
1
1
0
.
.
.
0
0
1
1
R1
DIVIDE RATIO
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
0
1
.
.
.
0
1
0
1
1
2
3
4
.
.
.
0
TEST MODE
BIT SHOULD
BE SET TO 0
0
.
.
FOR NORMAL
OPERATION.
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
.
1
1
1
1
16380
16381
16382
16383
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH
0
0
1
1
0
1
0
1
3.0ns
1.3ns
6.0ns
3.0ns
LDP
0
LOCK DETECT PRECISION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
0
0
1
1
0
1
0
1
1
2
4
8
Rev. C | Page 15 of 24
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