ADF4106
Data Sheet
Parameter
B Version1 B Chips2 (typ) Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
–223
−122
–223
−122
dBc/Hz typ
dBc/Hz typ
PLL loop B/W = 500 kHz, measured at 100 kHz
offset
10 kHz offset; normalized to 1 GHz
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 1 MHz PFD frequency
11
(PNSYNTH
)
Normalized 1/f Noise (PN1_f)12
Phase Noise Performance13
900 MHz14
–92.5
−76.5
−83.5
−92.5
−76.5
−83.5
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
5800 MHz15
5800 MHz16
Spurious Signals
900 MHz14
–90/–92
–65/–70
–70/–75
–90/–92
–65/–70
–70/–75
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 1 MHz/2 MHz and 1 MHz PFD frequency
5800 MHz15
5800 MHz16
1 Operating temperature range (B Version) is –40°C to +85°C.
2 The B chip specifications are given as typical values.
3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4 AVDD = DVDD = 3 V.
5 AC coupling ensures AVDD/2 bias.
6 Guaranteed by design. Sample tested to ensure compliance.
7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.
8 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.
9 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.
10 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.
11 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
12 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
13 The phase noise is measured with the EV-ADF4106SD1Z evaluation board and the Agilent E4440A Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
14
f
f
f
= 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz.
= 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz.
REFIN
REFIN
REFIN
15
16
TIMING CHARACTERISITICS
AVDD = DVDD = 3 V ꢀ10% AVDD ≤ VP ≤ 5.5 V% AGND = DGND = CPGND = 1 V% RSET = 5.ꢀ kΩ% dBm referred to 51 Ω% TA = TMAX to TMIN
%
unless otherwise noted.
Table 2.
Parameter
Limit1 (B Version)
Unit
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
CLOCK to LE Setup Time
LE Pulse Width
1 Operating temperature range (B Version) is –40°C to +85°C.
Rev. E | Page 4 of 24
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