Data Sheet
ADF4106
SPECIFICATIONS
AVDD = DVDD = 3 V ꢀ10% AVDD ≤ VP ≤ 5.5 V% AGND = DGND = CPGND = 1 V% RSET = 5.ꢀ kΩ% dBm referred to 51 Ω% TA = TMAX to TMIN
%
unless otherwise noted.
Table 1.
Parameter
B Version1 B Chips2 (typ) Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN)
See Figure 18 for input circuit
For lower frequencies, ensure
slew rate (SR) > 320 V/μs
0.5/6.0
0.5/6.0
GHz min/max
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
–10/0
300
–10/0
300
dBm min/max
MHz max
P = 8
325
325
MHz max
P = 16
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency6
CHARGE PUMP
20/300
0.8/VDD
10
20/300
0.8/VDD
10
MHz min/max
For f < 20 MHz, ensure SR > 50 V/μs
V p-p min/max Biased at AVDD/2 (see Note 55)
pF max
μA max
100
100
104
104
MHz max
ABP = 0, 0 (2.9 ns antibacklash pulse width)
Programmable, see Table 9
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
5
5
mA typ
μA typ
% typ
kΩ typ
nA max
% typ
With RSET = 5.1 kΩ
625
2.5
3.0/11
2
625
2.5
3.0/11
2
With RSET = 5.1 kΩ
See Table 9
1 nA typical; TA = 25°C
0.5 V ≤ VCP ≤ VP − 0.5 V
2
2
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
1.5
2
1.5
2
% typ
% typ
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
1.4
0.6
1
1.4
0.6
1
V min
V max
μA max
pF max
10
10
VOH, Output High Voltage
1.4
1.4
V min
Open-drain output chosen, 1 kΩ pull-up
resistor to 1.8 V
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
VDD − 0.4
100
0.4
VDD − 0.4
100
0.4
V min
μA max
V max
CMOS output chosen
IOL = 500 μA
POWER SUPPLIES
AVDD
DVDD
VP
2.7/3.3
AVDD
AVDD/5.5
11
11.5
13
2.7/3.3
AVDD
AVDD/5.5
9.0
9.5
10.5
0.4
V min/V max
V min/V max
mA max
mA max
mA max
mA max
μA typ
AVDD ≤ VP ≤ 5.5V
9.0 mA typ
9.5 mA typ
10.5 mA typ
TA = 25°C
IDD7 (AIDD + DIDD)
IDD8 (AIDD + DIDD)
IDD9 (AIDD + DIDD)
IP
Power-Down Mode10
(AIDD + DIDD)
0.4
10
10
Rev. E | Page 3 of 24
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