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ADF4106BRUZ-R7 参数 Datasheet PDF下载

ADF4106BRUZ-R7图片预览
型号: ADF4106BRUZ-R7
PDF下载: 下载PDF文件 查看货源
内容描述: PLL频率合成器 [PLL Frequency Synthesizer]
分类和应用:
文件页数/大小: 24 页 / 361 K
品牌: ADI [ ADI ]
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Data Sheet  
ADF4106  
APPLICATIONS  
LOCAL OSCILLATOR FOR LMDS BASE STATION  
TRANSMITTER  
Loop Bandwidth = 50 kHz  
FPFD = 1 MHz  
Figure 22 shows the ADF4106 being used with a VCO to  
produce the LO for an LMDS base station.  
N = 5800  
Extra Reference Spur Attenuation = 10 dB  
The reference input signal is applied to the circuit at FREFIN  
and, in this case, is terminated in 50 Ω. A typical base station  
system would have either a TCXO or an OCXO driving the  
reference input without any 50 Ω termination.  
These specifications are needed and used to derive the loop  
filter component values shown in Figure 22.  
The circuit in Figure 22 shows a typical phase noise  
performance of −83.5 dBc/Hz at 1 kHz offset from the carrier.  
Spurs are better than −62 dBc.  
To achieve a channel spacing of 1 MHz at the output, the  
10 MHz reference input must be divided by 10, using the  
on-chip reference divider of the ADF4106.  
The loop filter output drives the VCO, which in turn is fed  
back to the RF input of the PLL synthesizer and also drives the  
RF output terminal. A T-circuit configuration provides 50 Ω  
matching between the VCO output, the RF output, and the RFIN  
terminal of the synthesizer.  
The charge pump output of the ADF4106 (Pin 2) drives the  
loop filter. In calculating the loop filter component values, a  
number of items need to be considered. In this example, the  
loop filter was designed so that the overall phase margin for  
the system would be 45°.  
In a PLL system, it is important to know when the system  
is in lock. In Figure 22, this is accomplished by using the  
MUXOUT signal from the synthesizer. The MUXOUT pin  
can be programmed to monitor various internal signals in the  
synthesizer. One of these is the LD or lock-detect signal.  
Other PLL system specifications include:  
KD = 2.5 mA  
KV = 80 MHz/V  
V
V
P
DD  
RF  
OUT  
100pF  
18  
18Ω  
16  
7
15  
100pF  
14  
18Ω  
V
P
CP  
AV  
DV  
6.2kΩ  
DD  
DD  
10  
V
CC  
1000pF  
1000pF  
2
2
FREF  
8
IN  
REF  
IN  
20pF  
100pF  
4.3kΩ  
51Ω  
V956ME03  
ADF4106  
1, 3, 4, 5, 7, 8,  
9, 11, 12, 13  
1.5nF  
CE  
LOCK  
DETECT  
MUXOUT  
14  
CLK  
DATA  
LE  
100pF  
6
5
RF  
RF  
A
B
IN  
R
1
SET  
51Ω  
IN  
5.1kΩ  
100pF  
3
4
9
NOTE  
DECOUPLING CAPACITORS (0.1  
OF THE ADF4106 AND ON V OF THE V956ME03 HAVE  
µ
CC  
F/10pF) ON AV , DV , AND  
DD DD  
V
P
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.  
Figure 22. Local Oscillator for LMDS Base Station  
Rev. E | Page 19 of 24