ADE7761A
Table 6. F1–4 Frequency Selection
Note that if the on-chip reference is used, actual output
frequencies can vary from device to device due to a reference
tolerance of 8%.
S1
S0
F1–4 (Hz)1
1.72
F1−4 = OSC/2n 2
OSC/218
0
0
0
1
3.44
OSC/217
1
0
6.86
OSC/216
OSC/215
5.70× 0.66 × 0.66 ×1.72Hz
F − F2 Frequency =
= 0.34Hz
1
2 × 2 ×2.52
1
1
13.7
1 Values are generated using the nominal frequency of 450 kHz.
2 F1–4 are a binary fraction of the master clock and, therefore, vary with the
internal oscillator frequency (OSC).
CF Frequency = F1 − F2 × 64 = 22.0 Hz
As can be seen from these two example calculations, the
maximum output frequency for ac inputs is always half of that
for dc input signals. Table 8 shows a complete listing of all
maximum output frequencies for ac signals.
Frequency Output CF
The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the F1–4
frequency selected, the higher the CF scaling. Table 7 shows
how the two frequencies are related, depending on the states of
the logic inputs S0, S1, and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous active power. As with F1 and F2, the
frequency is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is high,
this active power information is accumulated over a much
shorter time. Therefore, less averaging is carried out in the
digital-to-frequency conversion. With much less averaging of
the active power signal, the CF output is much more responsive
to power fluctuations (see Figure 22).
Table 8. Maximum Output Frequencies on CF, F1, and F2 for
AC Inputs
F1, F2 Maximum CF Maximum
CF-to-
SCF S1 S0 Frequency (Hz)
Frequency (Hz) F1 Ratio
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0.34
0.34
0.68
0.68
1.36
1.36
2.72
2.72
43.52
21.76
43.52
21.76
43.52
21.76
43.52
5570
128
64
64
32
32
16
16
2048
FAULT DETECTION
Table 7. Relationship Between CF and F1, F2 Frequency
Outputs
The ADE7761A incorporates a novel fault detection scheme
that warns of fault conditions and allows the ADE7761A to
continue accurate billing during a fault event. The ADE7761A
does this by continuously monitoring both the phase and
neutral (return) currents. A fault is indicated when these
currents differ by more than 6.25%. However, even during a
fault, the output pulse rate on F1 and F2 is generated using the
larger of the two currents. Because the ADE7761A looks for a
difference between the voltage signals on V1A and V1B, it is
important that both current transducers be closely matched.
SCF
S1
S0
F1–4 (Hz)
CF Frequency Output
128 × F1, F2
64 × F1, F2
1
0
0
0
0
0
1.72
1.72
1
0
1
3.44
64 × F1, F2
0
0
1
3.44
32 × F1, F2
1
1
0
6.86
32 × F1, F2
0
1
0
6.86
16 × F1, F2
1
1
1
13.7
16 × F1, F2
0
1
1
13.7
2048 × F1, F2
On power-up, the output pulse rate of the ADE7761A is
proportional to the product of the voltage signals on V1A and
Channel 2. If the difference between V1A and V1B on power-up is
greater than 6.25%, the fault indicator (FAULT) becomes active
after about 1 sec. In addition, if V1B is greater than V1A, the
ADE7761A selects V1B as the input. The fault detection is
automatically disabled when the voltage signal on Channel 1 is
less than 0.3% of the full-scale input range. This eliminates false
detection of a fault due to noise at light loads.
Example
In this example, if ac voltages of 660 mV peak are applied to
V1 and V2, then the expected output frequency on CF, F1, and
F2 is calculated as
Gain = 1, PGA = 0
F
1–4 = 1.7 Hz, SCF = S1 = S0 = 0
V1rms = rms of 660 mV peak ac = 0.66/√2 V
V2rms = rms of 660 mV peak ac = 0.66/√2 V
VREF = 2.5 V (nominal reference value)
Rev. 0 | Page 17 of 24
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