ADE7759
(AV = DV = 5 V ꢃ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, TMIN to TMAX = –40ꢂC to +85ꢂC unless otherwise noted.)
DD
DD
TIMING CHARACTERISTICS1, 2
Parameter
A, B Versions
Unit
Test Conditions/Comments
Write Timing
t1
t2
t3
t4
t5
t6
t7
t8
20
150
150
10
5
6.4
4
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
µs (min)
µs (min)
ns (min)
CS Falling Edge to First SCLK Falling Edge
SCLK Logic High Pulsewidth
SCLK Logic Low Pulsewidth
Valid Data Setup Time Before Falling Edge of SCLK
Data Hold Time After SCLK Falling Edge
Minimum Time between the End of Data Byte Transfers
Minimum Time between Byte Transfers During a Serial Write
CS Hold Time After SCLK Falling Edge
100
Read Timing
t9
4
µs (min)
Minimum Time between Read Command (i.e., a Write to Communications
Register) and Data Read
t10
t11
4
30
µs (min)
Minimum Time between Data Byte Transfers During a Multibyte Read
Data Access Time After SCLK Rising Edge following a Write to the Communi-
cations Register
3
ns (min)
4
t12
100
10
100
ns (max)
ns (min)
ns (max)
ns (min)
Bus Relinquish Time After Falling Edge of SCLK
4
t13
Bus Relinquish Time After Rising Edge of CS
10
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
2See Figures 2 and 3 and Serial Interface section of this data sheet.
3Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
I
200ꢄA
OL
TO
OUTPUT
PIN
2.1V
C
50pF
L
1.6mA
I
OH
Figure 1. Load Circuit for Timing Specifications
t8
CS
t2
t6
t1
t3
t7
t7
SCLK
t4
t5
DIN
1
0
0
A4
A3
A2 A1
A0
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
CS
t1
t13
t9
t10
SCLK
DIN
0
0
0
A4
A3
A2 A1
A0
t12
t11
t11
DOUT
DB0
DB7
DB0
DB7
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 3. Serial Read Timing
–5–
REV. 0
ADI [ ADI ]
