AD9959
In single-bit serial mode, 2-wire interface operation, the
SERIAL I/O MODES OF OPERATION
SDIO_0 pin is the single serial data I/O pin. In single-bit serial
mode 3-wire interface operation, the SDIO_0 pin is the serial
data input pin and the SDIO_2 pin is the output data pin.
Regardless of the number of wires used in the interface, the
SDIO_3 pin is configured as an input and operates as the
SYNC_I/O pin in the single-bit serial mode and 2-bit serial
mode. The SDIO_1 pin is unused in this mode (see Table 26).
The following are the four programmable modes of serial I/O
port operation:
•
•
•
•
Single-bit serial 2-wire mode (default mode)
Single-bit serial 3-wire mode
2-bit serial mode
4-bit serial mode (SYNC_I/O not available)
2-Bit Serial Mode
Table 26 displays the function of all six serial I/O interface pins,
depending on the mode of serial I/O operation programmed.
The SPI port operation in 2-bit serial mode is identical to the
SPI port operation in single-bit serial mode, except that two bits
of data are registered on each rising edge of SCLK. Therefore, it
only takes four clock cycles to transfer eight bits of information.
The SDIO_0 pin contains the even numbered data bits using
the notation D[7:0], and the SDIO_1 pin contains the odd
numbered data bits. This even and odd numbered pin/data
alignment is valid in both MSB and LSB first formats (see
Figure 44).
Table 26. Serial I/O Port Pin Function vs. Serial I/O Mode
Single-Bit
Serial 2-Wire
Mode
Single-Bit
Serial 3-Wire
Mode
2-Bit
Serial
Mode
4-Bit
Serial
Mode
Pin
SCLK
Serial clock
Serial clock
Serial clock Serial
clock
CS
Chip select
Chip select
Chip select
Chip
select
SDIO_0 Serial data I/O Serial data in
Serial data
I/O
Serial
data I/O
4-Bit Serial Mode
SDIO_1 Not used for
SDIO1
SDIO_2 Not used for
SDIO1
Not used for
SDIO1
Serial data
out (SDO)
Serial data
I/O
Not used
for SDIO1
Serial
data I/O
Serial
data I/O
Serial
data I/O
The SPI port in 4-bit serial mode is identical to the SPI port in
single-bit serial mode, except that four bits of data are registered
on each rising edge of SCLK. Therefore, it takes only two clock
cycles to transfer eight bits of information. The SDIO_0 and
SDIO_2 pins contain even numbered data bits using the notation
D[7:0], and the SDIO_0 pin contains the LSB of the nibble. The
SDIO_1 and SDIO_3 pins contain the odd numbered data bits,
and the SDIO_1 pin contains the LSB of the nibble to be accessed.
SDIO_3 SYNC_I/O
SYNC_I/O
SYNC_I/O
1 In serial mode, these pins (SDIO_0/SDIO_1/SDIO_2/SDIO_3) can be used for
RU/RD operation.
The two bits in the channel select register, CSR[2:1], set the
serial I/O mode of operation and are defined in Table 27.
Note that when programming the device for 4-bit serial mode,
it is important to keep the SDIO_3 pin at Logic 0 until the device is
programmed out of the single-bit serial mode. Failure to do so
can result in the serial I/O port controller being out of sequence.
Table 27. Serial I/O Mode of Operation
Serial I/O Mode Select
(CSR[2:1])
Mode of Operation
Figure 43 through Figure 45 represent write timing diagrams
for each of the serial I/O modes available. Both MSB and LSB
first modes are shown. LSB first bits are shown in parentheses.
The clock stall low/high feature shown is not required. It is used
to show that data (SDIO) must have the proper setup time
relative to the rising edge of SCLK.
00
01
10
11
Single-bit serial mode (2-wire mode)
Single-bit serial mode (3-wire mode)
2-bit serial mode
4-bit serial mode
Single-Bit Serial (2-Wire and 3-Wire) Modes
The single-bit serial mode interface allows read/write access to
all registers that configure the AD9959. MSB first or LSB first
transfer formats are supported. In addition, the single-bit serial
mode interface port can be configured either as a single pin I/O,
which allows a 2-wire interface, or as two unidirectional pins
for input/output, which enable a 3-wire interface. Single-bit
mode allows the use of the SYNC_I/O function.
Figure 46 through Figure 49 represent read timing diagrams for
each of the serial I/O modes available. Both MSB and LSB first
modes are shown. LSB first bits are shown in parentheses. The
clock stall low/high feature shown is not required. It is used to
show that data (SDIO) must have the proper setup time relative
to the rising edge of SCLK for the instruction byte and the read
data that follows the falling edge of SCLK.
Rev. B | Page 33 of 44
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