AD9959
SERIAL I/O PORT
Phase 2 of the I/O cycle consists of the actual data transfer
OVERVIEW
(write/read) between the serial port controller and the serial
port buffer. The number of bytes transferred during this phase
of the communication cycle is a function of the register being
accessed. The actual number of additional SCLK rising edges
required for the data transfer and instruction byte depends on
the number of bytes in the register and the serial I/O mode of
operation.
The AD9959 serial I/O port offers multiple configurations to
provide significant flexibility. The serial I/O port offers an SPI-
compatible mode of operation that is virtually identical to the
SPI operation found in earlier Analog Devices DDS products.
The flexibility is provided by four data pins (SDIO_0, SDIO_1,
SDIO_2, SDIO_3) that allow four programmable modes of
serial I/O operation.
For example, when accessing Function Register 1 (FR1), which
is three bytes wide, Phase 2 of the I/O cycle requires that three
bytes be transferred. After transferring all data bytes per the
instruction byte, the communication cycle is completed for that
register.
Three of the four data pins (SDIO_1, SDIO_2, SDIO_3) can be
used for functions other than serial I/O port operation. These pins
can also be used to initiate a ramp-up or ramp-down (RU/RD)
of the 10-bit amplitude output scalar. In addition, SDIO_3 can
be used to provide the SYNC_I/O function that resynchronizes
the serial I/O port controller if it is out of proper sequence.
At the completion of a communication cycle, the AD9959 serial
port controller expects the next set of rising SCLK edges to be
the instruction byte for the next communication cycle. All data
written to the AD9959 is registered on the rising edge of SCLK.
Data is read on the falling edge of SCLK (see Figure 43 through
Figure 49). The timing specifications for Figure 41 and Figure 42
are described in Table 25.
The maximum speed of the serial I/O port SCLK is 200 MHz,
but the four data pins (SDIO_0, SDIO_1, SDIO_2, SDIO_3)
can be used to further increase data throughput. The maximum
data throughput using all the SDIO pins (SDIO_0, SDIO_1,
SDIO_2, SDIO_3) is 800 Mbps.
Note that all channels share Register 0x03 to Register 0x18, which
are shown in the Register Maps and Bit Descriptions section.
This address sharing enables all four DDS channels to be written
to simultaneously. For example, if a common frequency tuning
word is desired for all four channels, it can be written once
through the serial I/O port to all four channels. This is the
default mode of operation (all channels enabled). To enable
each channel to be independent, the four channel enable bits
found in the channel select register (CSR, Register 0x00) must
be used.
tPRE
tSCLK
CS
tDSU
tSCLKPWL
SCLK
tSCLKPWH
tDHLD
SDIO_x
Figure 41. Setup and Hold Timing for the Serial I/O Port
CS
There are effectively four sets or copies of addresses (Register 0x03
to Register 0x18) that the channel enable bits can access to provide
channel independence. See the Descriptions for Control Registers
section for further details of programming channels that are
common to or independent from each other. To properly read
back Register 0x03 to Register 0x18, the user must enable only
one channel enable bit at a time.
SCLK
SDIO_x
SDO (SDIO_2)
tDV
Figure 42. Timing Diagram for Data Read for Serial I/O Port
Table 25. Timing Specifications
Serial operation of the AD9959 occurs at the register level,
not the byte level% that is, the controller expects that all bytes
contained in the register address are accessed. The SYNC_I/O
function can be used to abort an I/O operation, thereby allowing
fewer than all bytes to be accessed. This feature can be used to
program only a part of the addressed register. Note that only
completed bytes are affected.
Parameter Min Unit
Description
tPRE
1.0
5.0
2.2
2.2
1.6
0
ns min CS setup time
tSCLK
tDSU
tSCLKPWH
tSCLKPWL
tDHLD
tDV
ns min Period of serial data clock
ns min Serial data setup time
ns min Serial data clock pulse width high
ns min Serial data clock pulse width low
ns min Serial data hold time
ns min Data valid time
There are two phases to a serial communications cycle. Phase 1
is the instruction cycle, which writes the instruction byte into
the AD9959. Each bit of the instruction byte is registered on
each corresponding rising edge of SCLK. The instruction byte
defines whether the upcoming data transfer is a write or read
operation. The instruction byte contains the serial address of
the address register.
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Rev. B | Page 31 of 44
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