AD9883A
Analog Interface
(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)
Test
AD9883ABST–110
AD9883ABST–140
Parameter
Temp Level Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
I
VI
I
0.5
0.5
+1.25/–1.0
+1.5/–1.0
1.85
0.5
0.5
+1.5/–1.0
+1.81/–1.0
1.85
LSB
LSB
LSB
LSB
Integral Nonlinearity
VI
3.2
3.2
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Full
Full
25°C
VI
VI
V
0.5
0.5
V p-p
V p-p
ppm/°C
µA
1.0
1.0
100
100
Input Bias Current
25°C IV
1
2
75
8.0
52
1
2
75
10.0
52
Full
Full
Full
Full
IV
VI
VI
VI
µA
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
7
1.5
49
7
1.5
49
mV
% FS
% FS
46
46
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Full
Full
VI
V
1.19
1.25
100
1.33
1.19
1.25
100
1.33
V
ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
110
140
MSPS
MSPS
ns
10
+2.0
10
+2.0
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
µs
µs
µs
µs
µs
µs
µs
µs
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
110
110
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
110
140
12
12
25°C IV
Full
Full
400
15
7001
11001
400
15
7001
11001
IV
IV
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
Full
Full
Full
Full
VI
VI
V
2.5
2.5
V
V
µA
µA
pF
0.8
–1.0
1.0
0.8
–1.0
1.0
V
+25°C V
3
3
DIGITAL OUTPUTS
Output Voltage, High (VOH
Output Voltage, Low (VOL
Duty Cycle, DATACK
Output Coding
)
)
Full
Full
Full
VI
VI
IV
VD – 0.1
45
VD – 0.1
45
V
V
%
0.1
55
0.1
55
50
Binary
50
Binary
–4–
REV. B
ADI [ ADI ]
